UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant benu
Participant
154 Views
Registered: ‎06-09-2014

VC707 PCIE link width

Hello,

I've been trying to use the PCIe XDMA core with the VC707 (Vivado 2017.4), the link comes up as gen2 but only x1 link width (link cap: 5 GT/s x8, link sta: 5 GT/s x1)

I've switched to using the Xilinx VC707 PCIe reference design (XTP 207) for debugging purposes.

My motherboard has plenty of pcie lanes so that is not the issue. I've plugged in other pcie cards in the same slot and had them come up as x8.

I've tried 2 gen3 motherboards and 2 different gen3 switches. It always comes up default as x1, but if i use the directed PCIE link width change i can get it to change to gen2 x2 but never any higher link width. I've moved the PCIE prsnt jumper around and it should be on x8. I've run the IBERT on the banks 114, 115 where the PCIe edge lanes are with an external PCIe loopback and got connectivity between all TX/RX pairs and good BER.

 

Might there be incompatibility between gen3 motherboards and this gen2 pcie core?

Thanks,

Ben

0 Kudos