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Observer
Observer
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Registered: ‎05-31-2014

VC707 ddr3 issue with clock constraint - Vivado 2014.1

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Hello -

  I've been trying to create a microblaze design on the VC707 using Vivado 2014.1 and keep running into a critcal warning on the DDR3 Clk (output). I'm using the predefined DDR3 IP that was configured specifically for the board and I can get everything to validate. However when I try to build it, I always get the same critical warning from the DRC:

  IOSTDTYPE #1 Critical Warning I/O port ddr3_sdram_ck_n[0] is Single-Ended but has an IOStandard of DIFF_SSTL15 which can only support Differential
  IOSTDTYPE #2 Critical Warning I/O port ddr3_sdram_ck_p[0] is Single-Ended but has an IOStandard of DIFF_SSTL15 which can only support Differential

 

This implies that if I force Vivado to ignore the warning, the DDR3 clock will not get a proper differential driver for the DDR3 clock (which sounds like major issue).  


As far as I can tell, the pin mapping (G18 and H19) are fine.  What I'm I doing wrong?  


Andrew Dowd

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Observer
Observer
15,534 Views
Registered: ‎05-31-2014

Re: VC707 ddr3 issue with clock constraint - Vivado 2014.1

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Thanks for the info Vanitha.  

  As it turns out, this particular DRC message was suprious.    I was watching a Xilinx video about using  Vivado.  In the bottom of their Vivado display, you can clearly see the same DRC error highlighted in RED.    The Xilinx engineer just ignored it.   I went ahead and did the same.  I just build the project and it ran fime, including a self-test of the DDR3 memory.   The issue seems to be contained in the DRC, but the implementation does the right thing.

 

Regards

Andy 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: VC707 ddr3 issue with clock constraint - Vivado 2014.1

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Hi,

 

This warning or DRC error indicates there is no IBUFDS/IBUFGDS primitive connected to the differential input pads so the two pads are treated as single-ended. Although the IBUFDS has been instantiated in the HDL code, it could be removed during Synthesis or Implementation due to unconnenctivity. Check the schematic in Synthesized design or Implemented design to see if IBUFDS is in the netlist or not.

 

Also this issue can cause because of the nets that are connected to IBUFGDS does not drive any logic. So it get optimized while running opt_design.
If you want to prevent this pins from optimization you need to place a Dont touch constraint on it.
 
Hope this helps
 
Regards,
Vanitha
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Observer
Observer
15,535 Views
Registered: ‎05-31-2014

Re: VC707 ddr3 issue with clock constraint - Vivado 2014.1

Jump to solution

Thanks for the info Vanitha.  

  As it turns out, this particular DRC message was suprious.    I was watching a Xilinx video about using  Vivado.  In the bottom of their Vivado display, you can clearly see the same DRC error highlighted in RED.    The Xilinx engineer just ignored it.   I went ahead and did the same.  I just build the project and it ran fime, including a self-test of the DDR3 memory.   The issue seems to be contained in the DRC, but the implementation does the right thing.

 

Regards

Andy 

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