08-11-2015 06:51 PM
I'm clocking my GTX for SFP stm1 input on a clk_stm1 ~155.52MHz which is from the Si570 via the Si5324 to the GTX block
I'm not sure on ppm for this clk, how much it may be off.. the Si570 data sheet is very confusing to me on this as it appears to say the ppm increases over age of the chip correct? For first year new board what would my PPM expected be?
I'm trying to get a stm1 clk that meets the stm1 standards of I believe 4.5 ppm if I'm not wrong... wondering if the VC707 board with this clk meets this spec?
08-12-2015 09:25 AM
You need to configurae the Si5324 to start in free-run mode first at the targetted reference clock frequency and then output the recovered clock from the interface to the SI5324 and switch over to the that input to acheive the needed PPM tolerance.
08-12-2015 02:48 PM
Thanks - so I see now on the VC707 schematic the Si570 is 50PPM and the Si5324 114.285MHz ref XTL is 20 PPM.
I'm not clear on your response -
I'm guessing your saying I need to lock up the reference clock first (the
114.285MHz 20PPM crystal attached to the si5324) and then use that to improve the 155.52
clockin from my Si570 (that passes through V7 pins => IBUFDS => ODDR => OBUFDS => outpins to Si5324).
I followed the Si5324 data sheet closely and their Si software which spits out register settings which I use via I2c to setup the ability to lock on and pass through the stm1 rate from the Si570 that I'm feeding it.
So it appears my stm1 refclk is ok and clean - but your saying maybe when I configure the Si5324 on bootup I need to do an additional first step to lock to the 114.285MHzXTL first to improve the stm1 clk I pass through?
Why is this needed, what's the cons if I don't do this? Is it just to improve my 50 PPM clk to be more accurate to the actual stm1 rate?
Can you point me towards page on Si datasheet that talks of doing this?
08-12-2015 06:26 PM
Having the Si570 as a reference clock source for the Si5324 adds no value and I'm not even sure how you did this as the Si570 is not connected to the Si5324.
You only need to use the Si5324 in free run mode with the 114.285 MHz crystal to generate the initial 155.52 MHz for the GTHs to operate, lock and generate a recovered clock from the received data. See page 73, section 6.5 of the Si53xxReferenceManual for more information on the free run mode.
Once you have the GTH locked to the incoming data stream, the RXRECCLK can then be driven from the FPGA to the Si5324 using the REC_CLOCK_C_P|N pins and it will switch over and locked to the clock providing a 0 PPM offset.
The Si5324 data sheet has the necessary register information to enable the FREE_RUN mode and to set the priority for CKIN1 (recovered clock) vs CKIN2 (crystal). Note:CKIN1 should have priority over CKIN2, so that the Si5324 will automatically switch from the crystal to the receovered clock.