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Participant abhijithcd
Participant
1,481 Views
Registered: ‎06-22-2017

VC707 suggestion for clock and trigger output ports

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Hi all,

 

I have a VC707 Evaluation board. I need to forward a 'clock' output and a trigger data based on the same 'clock' out of the board.

I am planning to use USER SMA GPIO (J33, J34) and GTX transmitter SMA (TX) (J29/J30) to get the outputs.

 

I would like to know if these are the only options to get the data out? Can these ports be used interchangeably for either trigger or clock?

 

Thanks and Regards,

Abhijith

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Xilinx Employee
Xilinx Employee
2,041 Views
Registered: ‎06-02-2017

Re: VC707 suggestion for clock and trigger output ports

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Hi,

 

Yes, the user SMA ports can be used to forward both data and clock.

But in my understand, you need to forward a pair of data accompanied with  a pair of clock. That means you need at least 4 user SMA ports, while there are only two in most Xilinx boards. That's why I suggest you leverage FMC. 

Re: VC707 suggestion for clock and trigger output ... - Community Forums Xilinx.com

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5 Replies
Xilinx Employee
Xilinx Employee
1,466 Views
Registered: ‎08-01-2008

Re: VC707 suggestion for clock and trigger output ports

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You can use clock to drive an ODDR, then send the ODDR output to a spare pin and probe it up to a scope. Below is an example of how to drive an ODDR, where clk180 is just inverted version of clk0. 

 

ODDR2 #(
      .DDR_ALIGNMENT ("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
      .INIT          (1'b0),    // Sets initial state of the Q output to 1'b0 or 1'b1
      .SRTYPE        ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
   ) ODDR2_clk_o (
      .Q  (clk_o),   // 1-bit DDR output data
      .C0 (clk0),   // 1-bit clock input
      .C1 (clk180),   // 1-bit clock input
      .CE (1'b1), // 1-bit clock enable input
      .D0 (1'b1), // 1-bit data input (associated with C0)
      .D1 (1'b0), // 1-bit data input (associated with C1)
      .R  (1'b0),   // 1-bit reset input
      .S  (1'b0)    // 1-bit set input
 );
 

Thanks and Regards
Balkrishan
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Participant abhijithcd
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Registered: ‎06-22-2017

Re: VC707 suggestion for clock and trigger output ports

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@balkris Thanks for the reply.

 

Yes, I had seen that I need to interface the clock with an ODDR before sending it out.

But I need to send the clock and trigger outputs to an external ADC board.

So, I needed a clarification if I could use USER SMA GPIO (J33, J34) and GTX transmitter SMA (TX) (J29/J30) as my output ports?

Are there any other GPIO ports on VC707 that would serve the purpose?

 

Thanks and Regards,

Abhijith

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Xilinx Employee
Xilinx Employee
1,403 Views
Registered: ‎06-02-2017

Re: VC707 suggestion for clock and trigger output ports

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Hi,

 

I don't think you can leverage the SMA of GTX transmitter for your design. For this requirement, FMC is the best solution, but you need an extension board.

If the frequency of the signals are not high, you can consider to make some modifications with the board, such as wired out the pins connected to the switches on the board.

 

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Participant abhijithcd
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Registered: ‎06-22-2017

Re: VC707 suggestion for clock and trigger output ports

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Hi @zhiq

Thanks a lot for your reply.

May I know the reason why USER GPIO SMA cannot be used for the purpose of forwarding data?

 

I tried to forward data through it. I could see the waveforms on the oscilloscope. But some other signals on my FMC card are getting messed up because of this.

I am using LVCMOS18 IO standard and forwarding data through an ODDR and OBUF. 

 

Just curious to know the reason. Any clarification would be helpful

 

Thanks and Regards,

Abhijith

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Xilinx Employee
Xilinx Employee
2,042 Views
Registered: ‎06-02-2017

Re: VC707 suggestion for clock and trigger output ports

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Hi,

 

Yes, the user SMA ports can be used to forward both data and clock.

But in my understand, you need to forward a pair of data accompanied with  a pair of clock. That means you need at least 4 user SMA ports, while there are only two in most Xilinx boards. That's why I suggest you leverage FMC. 

Re: VC707 suggestion for clock and trigger output ... - Community Forums Xilinx.com

-------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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View solution in original post