cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
11,331 Views
Registered: ‎07-25-2013

VC709 Connectivity Kit - Reference Design using 10/40 GbE SFP+

Jump to solution

The Connectivity Kit VC709 has a number of excellent reference designs (avaible at AR# 55456) but none of them demonstrates the usage of the 10/40 GbE SPF+ capabilities.

 

On the board's design page (http://www.xilinx.com/products/boards-and-kits/EK-V7-VC709-CES-G.htm) there is a featured design with the diagram attached. Have looked around but couldn't find where to download this it. Anyone where it can be downloaded from?

 

Would be very grateful for any design that makes use of the EMAC+PCS/PMA on this board, and includes a working XDC file.

 

 

 

v7_connectivity_trd.jpg
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
16,567 Views
Registered: ‎07-31-2012

Hi,


The latest TRD files for Vivado 2013.2 release are as shown below.

 

1) TRD PDF

2) 2013.2 latest TRD Design Files

 

Use these files and please let me know in case of any queries.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

8 Replies
Highlighted
Xilinx Employee
Xilinx Employee
11,291 Views
Registered: ‎08-02-2007

Hi,

 

The TRD is in early access. Please refer this AR. http://www.xilinx.com/support/answers/55534.html

 

--HS

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
Highlighted
Xilinx Employee
Xilinx Employee
11,179 Views
Registered: ‎08-01-2012

Are you using VC709 early access (EA) design? Instead of trying on EA release (Which was not fully characterized) of early access VC709 the best option is that trying on officially released one which has tested & released VC709 reference designs for Vivado2013.2. The fully characterized official VC709 reference designs for Vivado2013.2 is already in releasing phase.

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

Highlighted
Visitor
Visitor
11,151 Views
Registered: ‎07-25-2013

Thank you for your reply.

 

Do you know where we could get hold of these VC709 "releasing phase" designs for Vivado 2013.2?

 

We have tried the EA TRD, but somehow there was an error somewhere due to some missing modules/licenses...

Still it was very useful as it demonstrated how to generate the 156MHz clock for the GTHE2 transceivers!

 

For now, we just want to try something very simple: send/receive an Ethernet frame to and from an Intel 10GbE NIC card (X520). We had a solution working on the ML605, using the 1GbE interface, and are now trying to upgrade this design to the V7 with the 10GbE NIC.

 

So far, we got a simulation test-bench to work using Xilinx's 10GbE PCS/PMA + EMAC cores with temporary licenses. However when we implement this core and program the FPGA, it simply does not behave as expected. 

 

Wondering if you would have any other simpler designs which achieves this simple task of RX/TX-ing an Ethernet frame to an outside NIC.

 

Thanks in advance.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
16,568 Views
Registered: ‎07-31-2012

Hi,


The latest TRD files for Vivado 2013.2 release are as shown below.

 

1) TRD PDF

2) 2013.2 latest TRD Design Files

 

Use these files and please let me know in case of any queries.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

Highlighted
Visitor
Visitor
11,135 Views
Registered: ‎07-25-2013

Got it to work :-)))

Thank you all for the documentation and the example designs!

/A

 

 

 

0 Kudos
Highlighted
Visitor
Visitor
10,889 Views
Registered: ‎09-25-2013

Could you provide working project with TRD?

With Vivado 2013.2 I get the following message:

 
"[Designutils 20-1365] Unable to generate target(s) for the following file is locked: c:/Anton/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.srcs/sources_1/ip/ten_gig_eth_mac_axi_st_ip/ten_gig_eth_mac_axi_st_ip.xci
Locked reason: IP 'ten_gig_eth_mac_axi_st_ip' requires a license but no valid license was found. No useable outputs are available for this IP. However license checkpoints may prevent use of this IP in some tool flows. Please select 'Report IP Status' from the 'Tools' menu for instructions to unlock.".
 
and
 
"[Designutils 20-1365] Unable to generate target(s) for the following file is locked: c:/Anton/v7_xt_conn_trd/vivado/project_1/xt_connectivity_trd.srcs/sources_1/ip/ten_gig_eth_pcs_pma_ip/ten_gig_eth_pcs_pma_ip.xci
Locked reason: IP 'ten_gig_eth_pcs_pma_ip' requires a license but no valid license was found. No useable outputs are available for this IP. However license checkpoints may prevent use of this IP in some tool flows. Please select 'Report IP Status' from the 'Tools' menu for instructions to unlock.
"
0 Kudos
Highlighted
Visitor
Visitor
10,877 Views
Registered: ‎09-25-2013
I got it working with 2013.2.
0 Kudos
Highlighted
Visitor
Visitor
10,669 Views
Registered: ‎02-24-2009

Anyone had any luck simulating this with Modelsim?  

 

I can simulate with Vivado but when I run the mti tcl script Modelsim (SE-64 10.1b) gives me "Error:...compare.vhd(46) in protected region".  Same if I use 10.3 

 

I thought model/questa supported IEEE1735?

 

 

0 Kudos