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Visitor first.fpga
Visitor
166 Views
Registered: ‎05-12-2018

VC709 +SYS_CLK

FOR HELP:

       I set clk as picture,but cannot receiver anyone clk .

snipaste_20190824_092019.png
snipaste_20190824_092031.png
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Xilinx Employee
Xilinx Employee
92 Views
Registered: ‎06-21-2018

Re: VC709 +SYS_CLK

Hi first.fpga,

IBUFGDS is not a valid primitive for 7 series FPGAs:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug953-vivado-7series-libraries.pdf

Can you try with IBUFDS instead and see if that fixes it?

Thanks,
Andres

 

 

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