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Newbie mbanna
Newbie
7,957 Views
Registered: ‎02-04-2014

VC7203 HP/HR IO Banks

Hi,

 

I have two questions about "VC7203 Characterization Kit" including "XC7VX485T-3 FFG1761E FPGA"

 

1. I see that the kit has: 200 MHz 2.5V LVDS Oscillator, that is connected to E18/E19 FPGA pins.

It is clear that E18/E19 is LVDS 2.5 "VCCO required is 2.5" but in the schematic they are part of BANK 38 which is supposed to be HP bank with VCCO = 1.8

 

According to ug471, all IOs per bank should have the same VCCO voltage, then can you clarify how E18, E19 are connected to HP bank?

 

2. FMC VADJ is connected to VCCO_HP. Does this mean that all FMC connector pins can be configured to LVCMOS18 or LVDS 18 ?

 

Thanks

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2 Replies
Xilinx Employee
Xilinx Employee
7,956 Views
Registered: ‎07-11-2011

Re: VC7203 HP/HR IO Banks

Hi,

 

200MHz is used for MIG reference clock but 2.5V is permitted with coupling network

For Q1 please refer this link http://www.xilinx.com/support/answers/40603.html

 

Q2.

http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/FMC-VADJ-HP-HR-and-7-series/td-p/202747

 

 

Hope this helps

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
7,933 Views
Registered: ‎01-03-2008

Re: VC7203 HP/HR IO Banks

> 1. I see that the kit has: 200 MHz 2.5V LVDS Oscillator, that is connected to E18/E19 FPGA pins.

> It is clear that E18/E19 is LVDS 2.5 "VCCO required is 2.5"

 

LVDS is always LVDS regardless of the voltage supply for a driver and it is always 1.25V +/- ~200mV. 

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