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Observer
Observer
7,596 Views
Registered: ‎09-20-2011

VCCINT power supply problem!?

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Hello,

 

After hours of debugging, I think I have found the problem.

I use a ML605 board connected to a host PC via PCIe.

My design runs on the Virtex-6 FPGA which contains up to 40 crypto cores running at 300 MHz. When the cores calculate only few crypto operations, everthing works fine. But if I choose longer vectors, the entire FPGA crashes. Even the JTAG does not work anymore until I power up the board again. It seems that the VCCINT power supply drops under the specified 0.95V (http://www.xilinx.com/support/answers/37667.html) on heavy load. I discovered the behavior by watching the min value of VCCINT via impact (Get Device ID).

 

Countermeasure I have already taken:

I devided my single crypto clock into 4 seperate crypto clocks with 90° phase shift to each other.

I also synthesized my design with power options enabled.

 

Nothing worked for me. So, which further steps I can take?

 

Thanks for your recommendations,

Bernhard

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Participant
Participant
11,854 Views
Registered: ‎07-03-2013

1. VCD will work fine as input to XPOWER;  there is a vcd2saif converter out there but you should not need it.

2. SSI Clocking is Spread Spectrum clocking, supported by the MMCMs in V6 by passing through a input clock with SSI, but your board needs to generated the shift.  Basically it is a wander in frequency and phase added to the clock to reduce EMI and switching noise.

3. I'm not a DES expert (Only a AES expert) but if there are functional blocks that are not in use every clock cycle you can partition the algorithm and clock gate those parts.  E.g. in AES, even with one ECB/Clock output rates, you can clock gate the entire Key Expansion logic after expansion to safe power.

4. Oh well ;(

5. Instantiating SYSMON and using it's outputs to switch a BUFGMUX to a lower frequency is actually not that complicated - you can generate the SYSMON from coregen with a user temperature or voltage threshold and then use its user alarm output to switch the BUFGMUX to a lower rate.

 

Good luck!

Digital Design Golden Rule: If its not tested - its broken.

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Participant
Participant
7,573 Views
Registered: ‎07-03-2013

Are those by chance SHA-256 Hashes for bitcoins...

 

  1. If you think you are exceeding the boards core power limits, I'd recommend capturing a SAIF file from a actual use case in simulation and playing this back through xpower to see whether the estimated FPGA power is reasonable for the board or not; plus it will give you a baseline to see if any changes affect power.
  2. Fixed phases wont reduce VCCINT/Ground Bounce issues much as your still dealing with clocks edges within ns of eachother, but you can try using SSI clocking (unique per clock) to see if you get any different results (less harmonic relationships)
  3. The only good way to reduce dynamic power in a V6 FPGA is to partition your design into seperate clock regions that can be dynamically gated as the logic is unused.  For best results you should use BUFH per region which limits a block of logic to a floorlanned two-adjacent-region. (See V6 UG363 for BUFHCE notes).  Or you can use BUFGCE but your limited then to the number of total buffers.   
  4. If your using lots of BRAMs, make sure to disable them when not in use to reduce power as well (same for other hard macros - e.g. DSPs).
  5. Lastly, you could put a SYSMON core inside the design and if you find that voltage and power are related, you can throttle some of the clocks down based on load.

Good luck.

Digital Design Golden Rule: If its not tested - its broken.
Observer
Observer
7,552 Views
Registered: ‎09-20-2011

Thanks for taking time to reply to my post.

 

Would be nice to get a few bitcoins but those are "only" DES cores :)

 

1) For the moment, I only manage to generate vcd-files with Modelsim. Do you have a hint for me, how to generate or convert it into SAIF?

 

2) I thought it would distribute the peak power consumtion ..

What is SSI clocking? ... I tried to google it but without success :(

 

3) I think clock gating would be not effective due to the fact that each crypto core calculates one result every clock cycle. I want to run all cores simultaneously to gain max performance.

 

4) Only 4 BRAMs are used by Xilinx's PCIe core.

 

5) Sounds like a lot of work :(

 

Now, I am lowering the frequency and number of cores and see, if the FPGA works reliably.

I have never expected that power supply could be an issue for an FPGA :/

-----------------------------------------------------------------------------------------
It's always good practice giving feedback, when description/solution/recommendation have been helpful!
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Participant
Participant
11,855 Views
Registered: ‎07-03-2013

1. VCD will work fine as input to XPOWER;  there is a vcd2saif converter out there but you should not need it.

2. SSI Clocking is Spread Spectrum clocking, supported by the MMCMs in V6 by passing through a input clock with SSI, but your board needs to generated the shift.  Basically it is a wander in frequency and phase added to the clock to reduce EMI and switching noise.

3. I'm not a DES expert (Only a AES expert) but if there are functional blocks that are not in use every clock cycle you can partition the algorithm and clock gate those parts.  E.g. in AES, even with one ECB/Clock output rates, you can clock gate the entire Key Expansion logic after expansion to safe power.

4. Oh well ;(

5. Instantiating SYSMON and using it's outputs to switch a BUFGMUX to a lower frequency is actually not that complicated - you can generate the SYSMON from coregen with a user temperature or voltage threshold and then use its user alarm output to switch the BUFGMUX to a lower rate.

 

Good luck!

Digital Design Golden Rule: If its not tested - its broken.

View solution in original post

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