The initial design with 1 MicroBlaze and 1 MIG work (meets timing). But when I introduce the 2nd MIG, the timing start to fail.
Here are the questions:
1) Is AXI for MIG stuck at 300MHz? Can I use a slower clock for its AXI?2) What changes do I need to make for this design to work?
MB to DDR MIGDesign
Update: I followed (partially) Chapter 5 tutorial in UG898 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug898-vivado-embedded-design.pdf), with similar configurations compared to old design. The only significant change is to use a clocking wizard to generate 100MHz clock for MicroBlaze (old design uses the 100MHz clock from MIG). Somehow there is no more timing issue. Not sure how it helps vivado to find the solution.
The old design also has false path (unsafe) in clock interaction report (seems like clock wizard within MIG). But not in new design. Shouldn't using a clock generated from MIG has the same effect as a separate clocking wizard?