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Registered: ‎05-14-2018

VCU128 programmable user clock

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I want to use a programmable user clock in VCU128 board. The board user interface shows five different programmable clocks as shown below.

vcu128_clock.PNG

All of these clocks are connected to GTY transceivers by default. How can I use one of those clocks as a single-ended programmable user clock?

Thank you for helping me with this issue.

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Registered: ‎09-15-2016

Hi @altug_bilkent 

I believe that in order to use these clocks which is connected to  GTY transceivers by default as single ended user clock, you need to fed the REF clocks to IBUFDS_GT-->BUFG.

Please find the list of all clock sources for VCU128 board below:

ref_cl.JPG

Hope this helps.

Regards
Rohit
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Moderator
Moderator
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Registered: ‎09-15-2016

Hi @altug_bilkent 

I believe that in order to use these clocks which is connected to  GTY transceivers by default as single ended user clock, you need to fed the REF clocks to IBUFDS_GT-->BUFG.

Please find the list of all clock sources for VCU128 board below:

ref_cl.JPG

Hope this helps.

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Registered: ‎05-14-2018

Thank you for the prompt response. 

I used IBUFDS_GTE4 => BUFG_GT  to generate a single-ended user clock (CLK) as follows.

IBUFDS_GTE4_inst : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0', -- Refer to Transceiver User Guide
REFCLK_HROW_CK_SEL => "00", -- Refer to Transceiver User Guide
REFCLK_ICNTL_RX => "00" -- Refer to Transceiver User Guide
)
port map (
O => gte_clk, -- 1-bit output: Refer to Transceiver User Guide
ODIV2 => odiv2, -- 1-bit output: Refer to Transceiver User Guide
CEB => '0', -- 1-bit input: Refer to Transceiver User Guide
I => SI5328_CLOCK1_C_P, -- 1-bit input: Refer to Transceiver User Guide
IB => SI5328_CLOCK1_C_N -- 1-bit input: Refer to Transceiver User Guide
);


BUFG_GT_inst : BUFG_GT
port map (
O => CLK, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CEMASK => '1', -- 1-bit input: CE Mask
CLR => '0', -- 1-bit input: Asynchronous clear
CLRMASK => '0', -- 1-bit input: CLR Mask
DIV => "000", -- 3-bit input: Dynamic divide Value
I => odiv2 -- 1-bit input: Buffer
);

I also connect the reference clock in XDC as follows.

set_property PACKAGE_PIN R41 [get_ports "SI5328_CLOCK1_C_N"] ;# Bank 134 - MGTREFCLK1N_134
set_property PACKAGE_PIN R40 [get_ports "SI5328_CLOCK1_C_P"] ;# Bank 134 - MGTREFCLK1P_134

create_clock -period 10 -name sys_clk -waveform {0 5.0} [get_ports "SI5328_CLOCK1_C_P"];

When I change the frequency of SI5328 REFCLK using the board user interface, the frequency of CLK also changes successfully.