01-04-2018 03:39 PM
Xilinx recently announced the Xilinx Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit which will be available on market soon.
The platform is very powerful for prototyping next-generation of UHD applications but it lacks an FMC or other connectors which might provide access to generic I/O pins.
Notwithstanding, the board features 4 DDR DIMM allowing up to 64GB of memory (each DIMM support up to 16GB). I’m wondering if one or two of those DIMM interfaces can be used to access generic I/O pins.
According to the UG1268, the DDR4 DIMM interfaces are “Four independent dual-rank DDR4 interfaces”, and “VCU1525 DDR4 memory interfaces adhere to the constraints guidelines documented in the ‘DDR3/DDR4 Design Guidelines’ section of the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150)”.
I don’t have much experience with the Memory IP/Controller, so I’m wondering if someone think the IP can have flexibility enough to allow to route generic I/O signals to the DDR4 interfaces?
01-05-2018 04:53 PM
The problem with routing generic signals to these DDR4 banks is that they will be directly connected from the FPGA to the DIMM slot and most likely will have limited probe points on the board. I haven't delved in to the schematic or board files for this but any application outside of the DDR4 will be extremely limited.
01-06-2018 09:08 AM
thank you for your reply.
I just want to make sure that is possible to route signals to DIMM slots.
I'm completely aware of such implication. The idea is to develop a DIMM-FMC hardware adapter/converter which attaches to the DIMM slot and presents a generic FMC connector for accessing generic I/O signals. Since DIMM interfaces are optimized for bandwidth and speed, any application without such "strict" speed requirements can use the same interface. Correct me if I'm wrong. Obviously the design of the hardware adapter/converter need to take several things into consideration.