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Registered: ‎12-13-2009

VGA input (AD9980) with DVI output (CH7301) at 1024x768@60Hz (XGA)

I've been trying to get video to pass through an XUPV5-LX110T (ML505) board using VGA as input and outputting through DVI, but can't get the AD9980 VGA input working. The DVI output has been tested and works, but VGA input is more troublesome. I've read the registers of the AD9980 and found that the sync signals are active as inputs from another computer and received by the AD9980. Something weird though, register 0x26 is telling me that the number of Hsyncs per Vsyncs is something like 1216. This number doesn't make sense to me, as it is more than 1024 and less than the 1344 for the whole frame as tells me.


I'm thinking that these syncs are the issue because the monitor that should be receiving the output is not even receiving any signal. Before, when testing only the DVI output, the monitor would at least turn on when the wrong signal was sent to it (like improper DE timing), but not display video of course. Clocks seem to be outputting correctly from the AD9980 to the CH7301's XCLK and XCLK* inputs. Has anybody been able to use XGA resolution in this setup? 


Here are my settings for the AD9980 at 1024x768@60Hz:


    /* (REG@, DATA, DEVICE_ADDR) */

write_iic(0x05, 0x40, AD9980_addr); // Red Gain

write_iic(0x06, 0x00, AD9980_addr);

write_iic(0x07, 0x40, AD9980_addr); // Green Gain

write_iic(0x08, 0x00, AD9980_addr);

write_iic(0x09, 0x40, AD9980_addr); // Blue Gain

write_iic(0x0A, 0x00, AD9980_addr);

write_iic(0x0B, 0x02, AD9980_addr); // Red Offset

write_iic(0x0C, 0x00, AD9980_addr);

write_iic(0x0D, 0x02, AD9980_addr); // Green Offset

write_iic(0x0E, 0x00, AD9980_addr);

write_iic(0x0F, 0x02, AD9980_addr); // Blue Offset

write_iic(0x10, 0x00, AD9980_addr);

write_iic(0x11, 0x20, AD9980_addr); // Sync Seperator Threshold

write_iic(0x16, 0x02, AD9980_addr); // Precoast

write_iic(0x17, 0x0A, AD9980_addr); // Postcoast

write_iic(0x18, 0x00, AD9980_addr);

// Use internal coast generated from VSYNC

write_iic(0x19, 0x04, AD9980_addr);

// Clamp placement 4 counts after HSYNC drops  

write_iic(0x1A, 0x20, AD9980_addr);

// Clamp duration is 36 counts 

write_iic(0x1B, 0x33, AD9980_addr);

// Clamp and Offset (auto-offset every 64 clamps)

write_iic(0x1C, 0xFF, AD9980_addr); // TestReg0

write_iic(0x1D, 0x78, AD9980_addr); // SOG Control

write_iic(0x1E, 0xA4, AD9980_addr); // Power (OR TRY 0x24)

write_iic(0x1F, 0x14, AD9980_addr);

// Output Select 1

write_iic(0x20, 0x97, AD9980_addr);

// Output Select 2: 2x pixel clk, filtered/regen'd Hsync

write_iic(0x21, 0x20, AD9980_addr); // Default

write_iic(0x22, 0x32, AD9980_addr); // Default

write_iic(0x23, 0x0A, AD9980_addr); // Sync Filter Window Width

write_iic(0x28, 0xBF, AD9980_addr); // TestReg1

write_iic(0x29, 0x02, AD9980_addr); // TestReg2

write_iic(0x2C, 0x00, AD9980_addr); // Offset Hold

write_iic(0x2D, 0xE8, AD9980_addr); // TestReg5

write_iic(0x2E, 0xE0, AD9980_addr); // TestReg6

//Analog 1024x768@60 (XGA)

write_iic(0x01, 0x54, AD9980_addr); // PLL Div MSB

write_iic(0x02, 0x00, AD9980_addr); // PLL Div LSB

write_iic(0x03, 0xA8, AD9980_addr); // VCO/CPMP 

write_iic(0x04, 0x80, AD9980_addr); // Phase Adjust

write_iic(0x12, 0x80, AD9980_addr); // Hsync Control

write_iic(0x13, 0x88, AD9980_addr);

// Hsync Duration = 136 counts for XGA


write_iic(0x14, 0x86, AD9980_addr); // Vsync Control

write_iic(0x15, 0x06, AD9980_addr);

// Vsync Duration = 6 counts for XGA 

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5 Replies
Registered: ‎12-13-2009

After working on this a bit more, I realized the number of hsyncs per vsyncs is actually 800. That is with a 1024x768 input. When I have time I will try inputting a resolution of 800x600@60Hz (SVGA). Has anybody got it working at the XGA resolution?


The only way I could make sense of 800 is that it equals everything except the 6 vsync pulses on the vertical timing according to 


I have simple VHDL written that passes the vsync and hsync outputs from the AD9980 to the CH7301 DVI Transmitter chip. I thought these signals would at least get the monitor to say it was receiving a signal, but no luck.


Any suggestions? 

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The 800 Hsyncs per vsync  you are getting is the  # of hsyncs for 640x480 which is the default resolution of xilinx TFT controller. .  I am having a similar problem getting 1024x768 to work on a ML509. Have you figured out a way to reconfigure the chrontel chip?

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Registered: ‎02-09-2011

could you tell me how did you driver the IC CH7301 with hardcore

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Registered: ‎11-05-2008

I am trying to get the VGA input to work but I am stuck at I2C communication ...

I am using the I2C core provided by EDK 12.1 and the accompanying driver, as far as I can tell the signal connections

are all fine. 

I am following the protocol for accessing the registers of the ADC chip, as requested by the data sheet. I get an acknowledge for the first write of the register address (the handler call-back function of the driver gets called) but not for the subsequent read

of the register value.


What I2C core and driver are you ladies and gentlemen using? have you modified anything on the board (e.g. extra pull-up registers)?  

Any hint is greatly appreciated. 




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Registered: ‎07-21-2009

Not only are you guilty of cross-posting the same question to two different threads and forums, but you've posted the same questions to dormant threads which are completely unrelated to your new topic.

Suggest you start a new thread.  If the topic is 'how to use I2C', it belongs in the 'IP - others' forum.  If the topic is 'how to use this development board', then it belongs in one of the development board forums, depending on whether the development board is a Xilinx product.

- Bob Elkind

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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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