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Observer hotak
Observer
192 Views
Registered: ‎06-13-2018

Valid Design Check Error!!!

valid design check have critical messages.  What's the solution ?


1.JPG

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2 Replies
Teacher xilinxacct
Teacher
189 Views
Registered: ‎10-23-2018

Re: Valid Design Check Error!!!

@hotak 

This solution may give you some insight... https://forums.xilinx.com/t5/Other-FPGA-Architectures/Error-BD-41-703-in-VIVADO/m-p/914828#M30549

Check your port config.

Hope that Helps
If so, Please mark as solution accepted. Kudos also welcomed. :-)

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Observer hotak
Observer
183 Views
Registered: ‎06-13-2018

Re: Valid Design Check Error!!!

I think that port conifg is right.
I attach my block design file .
Could you check it , please?
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