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Highlighted Visitor
309 Views
Registered: ‎04-09-2019

I have an original verilog code which utilized 1800 LUTs and 1400 Flipflops. Now I inserted some extra lines of code (state machine code) into the original verilod code. Expected result is more utilization of LUTs and FFs than the that of original values. But the problem is there is no increment in LUTs and FFs. They are same as original values. What might be the reason?

2 Replies
Highlighted Scholar
289 Views
Registered: ‎05-21-2015

Without seeing the code and digging into it, the obvious answer was that much of your new logic was driven by constant values and so weeded out by the optimization pass.

Dan

Highlighted Visitor
233 Views
Registered: ‎04-09-2019

Sir,

Two files have been attached. Obf1.txt is the original code. Obf2.txt is the file where extra code is inserted.

```Extra code inserted:
reg c=1'b0;
reg[3:0] code_word;
reg[3:0] present_state, next_state;
parameter S0 = 4'b0000, S1 =4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100 ,S5= 4'b0101, S6= 4'b0110, S7=4'b0111, S8=4'b1000, S9=4'b1001, S10=4'b1010, S11=4'b1011, S12=4'b1100, S13=4'b1101, S14=4'b1110, S15=4'b1111 ;

always @(posedge push or posedge RST_top)
begin
//if (dout !=1) begin
if (RST_top == 1)
present_state<= S0;
else
present_state<= next_state;
end
//end

always @(present_state or din or push)
begin
case(present_state)
S0: if(din == 1'b1) begin
next_state<= S13;
code_word<=4'b0011;
//dout<= 0;
end
else begin
next_state<= S10;
code_word<=4'b0110;

end

S10: if(din == 1'b1) begin
next_state<= S9;
code_word<=next_state | code_word;
//dout<= 0;
end
else begin
next_state<= S8;
code_word<=next_state & code_word;
end

S8: if(din == 1'b1) begin
next_state<= S12;
code_word<={next_state , code_word[2:0]};
end
else begin
next_state<= S14;
code_word<= ~code_word;
end

S9: if(din == 1'b1) begin
next_state<= S14;
code_word<={next_state[3:1] , din};
//dout<= 0;
end
else begin
next_state<= S13;

end

S14: begin
next_state<= S3;
code_word<={din , code_word[3:1]};
end

S13: begin
next_state<= S12;
code_word<= {code_word[1:0] , next_state[3:2]};
end

S12: begin
next_state<= S15;
code_word<=  {code_word , (~din) , code_word[1:0]};
//dout<= 0;
end

S15: begin
next_state<= S3;
code_word<=  {(~din) , code_word[2:0]};
c<= 1'b1;
end

S11: begin
next_state<= S7;

end

S3: if(din == 1'b1) begin
next_state<= S5;
//dout<= 0;
end
else next_state<= S2;

S2: if(din == 1'b1) begin
next_state<= next_state ^ code_word;
//dout<= 0;
end

S5: begin
next_state<= S7;

end

S7: begin
next_state<= S6;

end

S6: if(din == 1'b1) begin
next_state<= S1;
//dout<= 0;
end
else next_state<= S5;

S1: begin
next_state<= S2;

end

S4: begin
next_state<= S7;

end

default next_state<= S0;
endcase
end

// C2: Outputs
always @(c)
begin
if(c) begin
dout<=1;
//correct=S5;
end
else begin
//next_state<= S2;
dout<= 0;
end

end```