12-09-2009 06:15 AM
We're working on a project on wind energy conversion in which the controller is to be designed using fpga.We are using Spartan 3e FPGA.We are unable to access the analog output through the dac.The problem is that the outputs A and B are at 1.659V and B and C are at 1.27V every time i.e after downloading the code to board as well as on just switching on the supply. Here's what we've done:
*We've a properly simulated code for parallel to serial data conversion using VHDL,the data is sent like "XXXX12 bit code address(c3c2c1c0)command(s3s2s1s0)XXXXXXXX".This is the standard protocal to be followed given in the user guide.
*We've divided the C9 50Mhz clock to a 10kHz clock using a 9 bit counter.This clock is then used to send the serial input through MOSI(T4 pin) and also this clock is given to the U16 pin.
*Assigned the DAC_CS and the DAC_CLR pin each to a switch to switch between 1 and 0.
*Also disabled the other enable pins of the intervening devices like SPI_SSB to 1,AMP_CS to 1,AD_CONV to 0,SF_CE0 to 1 and FPGA_INIT_B to 1.
But no proper output.
I request you to please go through my process and clearly put the necessary corrections and steps to be followed to get the proper output as soon as possible as our project's been stuck at this juncture.
Arun Srikanth Peri.
12-09-2009 07:12 AM
it is very difficult to assist you from a distance on such a complex design and problem.
my guess is that you have an FPGA IO bank voltage problem.
I would recommend you to carefully read through the Spartan-3E userguide about the Input/Output bank structure.
if you cannot resolve your problem and it is essential to solve it for your project, you can always purchase titanium support: http://www.xilinx.com/support/services/titanium/index.htm
best of luck,
12-09-2009 01:40 PM
There are lot of things that could be wrong.
What debug have you done to verify that any portion of the design works? Have you at least verified with an oscilloscope that the data pins from the FPGA to the DAC are functioning?
12-10-2009 08:23 AM
1st, You need to realize that none of us have your schematics, so when
you say U16 pin or C9 it means almost nothing.
a) have you downloaded a very simple design so that you know that the compile/download
process works for you?
b) have you simulated to make sure your logic is correct?
c) what voltage levels does the DAC expect to run at? Do you have the proper IO voltage
applied to theFPGA bank.
d) you mention that the DAC_CS pin is connect to a switch. This sounds very wrong to me.
All the SPI devices I've worked with use the CS pin to frame the data. It is usually a dynamic
e) if you download a simple design that simply outputs your 10kHz clock to the SPI clock pin
as a free running clock, do you actually see a good quality clock on the pin? If not, you need to
figure out what's causing the problem.
I hope this helps get you started.
12-14-2009 05:20 AM
Thank you Dries,Mcgett and John for the response.I've gone through the user guide again and taken the design through all the possible steps to debug it.
Now there seems to be an improvement in the output but then the actual output is quite wavering in and around the vicinity of the actual expected value.Eg:If the expected analog output is 1.4V,the out through the DSO shows values ranging right from 0 to around 1.4 increasing in order and then getting back to 0.If the expected value is lesser,then the range is also smaller.
This is not expected since I'm giving just a constant digital input.
Is the problem because of interface of the serial data with the DAC?But for the same reason,the DAC_CS pin i.e. the conversion start pin of the DAC is kept low during the time of passing of the serial bits(32 bits)to the DAC and is high on after the 32 bits are passed.
Also as to debug I've checked whether the divided clock is working by giving the clock to an LED.The DAC_CS pin also changes dynamically now since its value is assigned in accordance with the protocol(not via a switch).
I think there should be no problem with the code since the simulation is perfectly upto what is expected.
Can there be any other solution for this?If possible can I get a sample code for interfacing a single digital input to the DAC?
Arun Srikanth Peri.
12-14-2009 07:55 AM
Is it possible that the DAC has a diagnostic mode that outputs a ramp function regardless of the
data that you send it? This is probably not the issue, but it may be worth looking at.
Are you sure you're sending the bits to the DAC in the proper order?
12-15-2009 09:27 AM
12-15-2009 09:37 AM
There are different variations of spi timing that use different clock edges, I believe. Have you checked
that your design provides proper data setup/hold around the active clock edge?