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saurabh_daimler
Observer
Observer
10,869 Views
Registered: ‎11-02-2011

Video Processing on Digilent Atlys

I am using a digilent atlys board which has a spartan 6 FPGA device on it. I need to setup the environment for video processing such that I can take video input from its HDMI input port ,  apply some logic on it (burnt on FPGA) and send it to the HDMI output port. I know how to generate a bitfile and load it on a FPGA but I am really new when it comes to setting up the environment. Can you give me some direction on this?

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joelby
Advisor
Advisor
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Registered: ‎10-05-2010

Can you please explain exactly what you mean by 'environment'?

 

You should study XAPP495 and the corresponding reference design if you're doing anything with HDMI on the Atlys.

 

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saurabh_daimler
Observer
Observer
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Registered: ‎11-02-2011

I meant how to provide the video stream from a HDMI input port to my design on FPGA and provide the output video stream to the HDMI oupt port. I am using system generator for obtaining a HDL netlist or a bitfile. The pdf you have provided is very helpful ! Thanks.

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saurabh_daimler
Observer
Observer
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Registered: ‎11-02-2011

@joelby - I read the XAPP495 and came across the 2x2 DVI matrix reference design. In this design we pass the input video stream to the output. As I have mentioned earlier, I am using system generator for obtaining the HDL netlist etc. I want to put the logic generated by the system generator between the  transmitter and the receiver (i.e. I want to do some processing in between - see figure 12 in the pdf). Is it possible to generate  .v file (in case of verilog) with the help of system generator that has the correct specified interface so that I can integrate it easily with the transmitter and the receiver ?

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saurabh_daimler
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Observer
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Registered: ‎11-02-2011

Or if there is an example file/module that can be placed between transmitter and receiver , please let me know.

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joelby
Advisor
Advisor
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Registered: ‎10-05-2010

I'm afraid that I don't know anything about System Generator and how to integrate it with Verilog modules. It would be fairly straightforward to do what you want in plain HDL. Maybe you could ask your question on the DSP Tools forum?

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saurabh_daimler
Observer
Observer
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Registered: ‎11-02-2011

@joelby - I will post on DSP forum. The members of my group have no HDL experience. I got another problem with xapp495 DVI matrix reference design which no one has answered. Can you please take out some time and go thorugh this as well :

 

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/xapp495-2x2-DVI-Matrix/td-p/190014

 

Thanks a ton!

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danarie
Newbie
Newbie
10,407 Views
Registered: ‎08-27-2012

Hi,
Did you succeed in this project? I'm trying to do the exact same thing on the atlys.
thank you.
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saurabh_daimler
Observer
Observer
10,251 Views
Registered: ‎11-02-2011

Yes. Please follow XAPP495. Run the examples and then integrate them with your logic.
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ksharma3
Visitor
Visitor
9,325 Views
Registered: ‎05-20-2013

Hi Saurabh,

 

I am trying to do exactly the same thing as a part of project. I followed the steps given in some of the posts in this forum and have been able to generate the bit file without any errors. All I am trying to do is input a 3d/2d video from a source to fpga. Also, I am using JTAG clock as the startup clock. Is there a way I can check if I am getting some valide data "IN" ? Also, I did install the jumpers but none of the LEDs on FPGA lit.
I would really appreciate if you could help.

 

Thanks,

Kanika

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