11-02-2011 08:27 AM
I am using a digilent atlys board which has a spartan 6 FPGA device on it. I need to setup the environment for video processing such that I can take video input from its HDMI input port , apply some logic on it (burnt on FPGA) and send it to the HDMI output port. I know how to generate a bitfile and load it on a FPGA but I am really new when it comes to setting up the environment. Can you give me some direction on this?
11-02-2011 11:20 PM
11-03-2011 01:36 AM
I meant how to provide the video stream from a HDMI input port to my design on FPGA and provide the output video stream to the HDMI oupt port. I am using system generator for obtaining a HDL netlist or a bitfile. The pdf you have provided is very helpful ! Thanks.
11-07-2011 03:49 AM
@joelby - I read the XAPP495 and came across the 2x2 DVI matrix reference design. In this design we pass the input video stream to the output. As I have mentioned earlier, I am using system generator for obtaining the HDL netlist etc. I want to put the logic generated by the system generator between the transmitter and the receiver (i.e. I want to do some processing in between - see figure 12 in the pdf). Is it possible to generate .v file (in case of verilog) with the help of system generator that has the correct specified interface so that I can integrate it easily with the transmitter and the receiver ?
11-14-2011 04:17 AM
I'm afraid that I don't know anything about System Generator and how to integrate it with Verilog modules. It would be fairly straightforward to do what you want in plain HDL. Maybe you could ask your question on the DSP Tools forum?
11-14-2011 10:40 AM - edited 11-14-2011 10:41 AM
@joelby - I will post on DSP forum. The members of my group have no HDL experience. I got another problem with xapp495 DVI matrix reference design which no one has answered. Can you please take out some time and go thorugh this as well :
Thanks a ton!
05-29-2013 10:58 AM
I am trying to do exactly the same thing as a part of project. I followed the steps given in some of the posts in this forum and have been able to generate the bit file without any errors. All I am trying to do is input a 3d/2d video from a source to fpga. Also, I am using JTAG clock as the startup clock. Is there a way I can check if I am getting some valide data "IN" ? Also, I did install the jumpers but none of the LEDs on FPGA lit.
I would really appreciate if you could help.