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Adventurer
Adventurer
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Registered: ‎06-23-2016

Virtex-6 DQ/DQS placement errors

Hello,

 

I am trying to use some parts of the Virtex-5 DDR PHY on the Virtex-6 of ML605 board, in particular the dq/dqs related modules. I have attached the schematics of these two modules. Note that I do not get any problems while implementing these modules on the Virtex-5.

 

When trying to place the dqs pins in Planahead, I get the following error:

 

"Could not legally place instance u_iobuf_dqs/IBUFDS at IOB_X2Y125 since it belongs to a shape containing instance u_bufio_dqs. The shape requires relative placement between u_iobuf_dqs/IBUFDS and u_bufio_dqs that cannot be honored because it would result in an invalid location for u_bufio_dqs."

 

I am not sure from where this error comes. At first the pins I used were not CC which I thought would cause the error but changing the pins didn't resolve the error. Replacing the BUFIO by a wire or BUFH is a temporary fix for this error but creates many other timing related errors. 

 

When trying to place the dq pins, I get another error related to the SR/REV pins the OLOGICs (w. ODDRs) that I cannot explain:

 

"Could not route the logical net: GND on site OLOGIC_X2Y131 to the load pin OUTFF.REV.

Please check your design to see if the pin has a legal route to its driver or loads."

 

I am not sure if it's related to the first error or not but I would really appreciate your help.

ml605_2.PNG
ml605.PNG
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2 Replies
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Adventurer
Adventurer
792 Views
Registered: ‎06-23-2016

Up, I am really struggling here, does anyone have an idea?

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Adventurer
Adventurer
743 Views
Registered: ‎06-23-2016

As a follow up question, as BUFIOs get me errors, is it possible to drive the clock input of the IDDR with the output of the IODELAY?

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