09-20-2018 02:58 PM - edited 09-20-2018 05:11 PM
I am trying to use some parts of the Virtex-5 DDR PHY on the Virtex-6 of ML605 board, in particular the dq/dqs related modules. I have attached the schematics of these two modules. Note that I do not get any problems while implementing these modules on the Virtex-5.
When trying to place the dqs pins in Planahead, I get the following error:
"Could not legally place instance u_iobuf_dqs/IBUFDS at IOB_X2Y125 since it belongs to a shape containing instance u_bufio_dqs. The shape requires relative placement between u_iobuf_dqs/IBUFDS and u_bufio_dqs that cannot be honored because it would result in an invalid location for u_bufio_dqs."
I am not sure from where this error comes. At first the pins I used were not CC which I thought would cause the error but changing the pins didn't resolve the error. Replacing the BUFIO by a wire or BUFH is a temporary fix for this error but creates many other timing related errors.
When trying to place the dq pins, I get another error related to the SR/REV pins the OLOGICs (w. ODDRs) that I cannot explain:
"Could not route the logical net: GND on site OLOGIC_X2Y131 to the load pin OUTFF.REV.
Please check your design to see if the pin has a legal route to its driver or loads."
I am not sure if it's related to the first error or not but I would really appreciate your help.