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Visitor ichiro.wahid
Visitor
9,104 Views
Registered: ‎05-13-2011

Virtex 6 ML605 Built-In Self Test demo problems

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Hi,

 

I'm trying to test out a new ML605 (rev D) evaluation kit and the BIST demos that came with the compact flash card to verify board functionality. None of the demos have worked at all so far. I followed the instructions when first starting up the board - setting DIP switches, installing + configuring the USB-to-UART bridge/Tera Term - in the Getting Started guide UG533. I set my port to COM2, and TeraTerm can connect to it, but no output shows up. I have a VGA monitor connected to the board as well to test DVI/VGA output, but that's always blank.

 

I tried reloading the compact flash card with contents of cf_image from the design files (rdf0017_13.1_c.zip), but no luck. I also used Impact to "download.bit" from the ready_for_download folder. Impact programmed the FPGA successfully, but still the demos didn't work.

 

After that, I followed the ML605 BIST guide (xtp056_13.1_c.pdf). I used SDK to program the FPGA with the system.bit file, the system_bd.bmm file, and initialized "bootloader" as the ELF in BRAM. It loaded successfully but still nothing. I tried connecting with xmd:

 

XMD% connect mb mdm

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE_CF
 2       64250093          10        XC6VLX240T

MicroBlaze Processor Configuration :
-------------------------------------
Version............................8.10.a
Optimization.......................Performance
Interconnect.......................PLB_v46
MMU Type...........................No_MMU
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........on
Instruction Cache Base Address.....0x50000000
Instruction Cache High Address.....0x5fffffff
Data Cache Support.................on
Data Cache Base Address............0x50000000
Data Cache High Address............0x5fffffff
Exceptions  Support................off
FPU  Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Data Cache Write-back Support......off
Fault Tolerance Support............off
Stack Protection Support...........off
 ERROR: MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properly
	UNABLE to STOP MicroBlaze

The RESET error worries me. But when I try to connect a second time, I get:

 

XMD% connect mb mdm

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE_CF
 2       64250093          10        XC6VLX240T
 ERROR: Could not detect MDM peripheral on hardware. Please check:
	1. If FPGA is configured correctly
	2. MDM Core is instantiated in the design

The mdm shows up in the system.mhs file connected to the plb and microblaze debug buses. I'm not sure what the deal is with the RESET error, or why it doesn't show up the second time. I checked the system.ucf file, it has

 

Net sys_rst_pin PULLUP;
Net sys_rst_pin LOC= H10 | IOSTANDARD=SSTL15;
## System level constraints
Net sys_rst_pin TIG;

and the active high reset agrees with the ML605 Hardware User Guide (UG534, pp 49-50).

 

I'm using all 13.1 tools on Vista 64-bit machine. I'm assuming the TeraTerm is connected to UART properly because 1) the SiLab USB-UART bridge shows up in my device manager and 2) TeraTerm doesn't complain about connecting to the COM port. I'm also fairly sure the CF is loading properly (the SystemACE status LED blinks at startup and then stays solid green). It's a 2 GB card by Transcend with FAT format (came with kit). Also I have Production version Virtex 6 FPGA (Manufacturer's ID = Xilinx xc6vlx240t, Version : 6) so I'm using the right design files ("C" and not "CES").

 

Any help on this would be great, I'd really appreciate it. Just running the startup demos is eating up design time...

 

Thanks!

 

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1 Solution

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Visitor ichiro.wahid
Visitor
5,322 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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hi, sorry for the delay but this was eventually solved. there was a cold joint for one of the power module's inputs (supplying the 3.3 V). we realized this after trying to use the user switches to turn on the leds but they never did. we used a voltmeter and turned out the switches weren't getting the right voltage. HTH

View solution in original post

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10 Replies
Xilinx Employee
Xilinx Employee
9,084 Views
Registered: ‎01-03-2008

Re: Virtex 6 ML605 Built-In Self Test demo problems

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The USB UART will enumerate with different COM port numbers. What is the reported number shown in the device manager?
------Have you tried typing your question into Google? If not you should before posting.
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Visitor ichiro.wahid
Visitor
9,079 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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It initially showed up as COM7, which is the port I configured TeraTerm to. But I manually changed it to COM2 later. TeraTerm didn't give me errors connecting to either.

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Xilinx Employee
Xilinx Employee
9,077 Views
Registered: ‎01-03-2008

Re: Virtex 6 ML605 Built-In Self Test demo problems

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Teraterm won't report any errors as there is no way to determine if something is connected to the port.

Setting the SiLabs USB UART to COM2 may be in conflict with a regular serial port in your system. I would suggest the following.

1) change back to COM7
2) reboot your pc to make sure that nothing is leftover from the previous settings
3) make sure that the USB Cable is connected to the UART port and not the JTAG port
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor ichiro.wahid
Visitor
9,072 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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Thanks for the suggestions, but still no luck. TeraTerm is still blank.

 

One thing I should note is my device manager didn't have Ports (COM & LPT) tree prior to installing SiLabs (its a laptop). I added it by "Adding Legacy Hardware" and selecting "Ports" and then "SiLabs CP210x USB to UART Bridge" as the device driver. I doubt this is the problem though, windows seems to "detect" the board fine (it refreshes the Ports tree in Device Manager when I connect/disconnect the board).

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Visitor pzeno
Visitor
9,046 Views
Registered: ‎05-15-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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I didn't see anywhere in you messages that you pressed the System ACE reset switch after bringing up the TeraTerm window and configuring the com port. Pressing the reset (SW3) is what brings up the display of options in the TeraTerm window.

 

 

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Visitor ichiro.wahid
Visitor
9,036 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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Sorry I didn't mention it, but I've tried this several times as well. Resetting the SystemACE doesn't cause any output to show up on the TeraTerm.

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Xilinx Employee
Xilinx Employee
9,025 Views
Registered: ‎01-03-2008

Re: Virtex 6 ML605 Built-In Self Test demo problems

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There is a small chance that something was damaged in shipment and since it is a new board you could return it for a replacement with a RMA.

 

But, my speculation is that it is something with your PC.  Have you tried another system?

 

What happens when you type into TeraTerm?

------Have you tried typing your question into Google? If not you should before posting.
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Visitor ichiro.wahid
Visitor
9,017 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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Nothing shows up when we type in TeraTerm. We've tried this on two laptops, one running Vista and another running Windows 7. We've switched between several COM ports as well.

 

I've also tried building a simple system of my own and a program in SDK that prints to RS232 (I've ensured RS232_Uart_1 are stdin/out). Nothing showed up on TeraTerm when I did this. Nor could I connect to microblaze through xmd - the "Please check: 1. FPGA is configured correctly 2. MDM Core is instantiated in the design" error came up again.

 

I also tried the base reference design demo (ml605_brd) for ethernet/image filtering. When I connected the board to my Vista laptop, several LEDs beside the ethernet jack on the board lit up: the DUP and 1000 lights were solid, and the Rx light blinked green. But when I tried connecting to a network interface through the gui, the status was "Not connected to FPGA". Also when I ran this demo gpio LEDS #2-8 and the LED beside the Centre user switch (LED DS16) lit up on the board, which I found a bit odd for an ethernet demo...

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Observer austind
Observer
8,928 Views
Registered: ‎01-20-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

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Was this ever resolved? I have the exact same problem.

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Visitor ichiro.wahid
Visitor
5,323 Views
Registered: ‎05-13-2011

Re: Virtex 6 ML605 Built-In Self Test demo problems

Jump to solution

hi, sorry for the delay but this was eventually solved. there was a cold joint for one of the power module's inputs (supplying the 3.3 V). we realized this after trying to use the user switches to turn on the leds but they never did. we used a voltmeter and turned out the switches weren't getting the right voltage. HTH

View solution in original post

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