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Registered: ‎01-16-2015

Virtex 6 ML605 board - DDR3 example design question

Hi All,


I will begin by stating my current objective. I would like to assign an AND operator two GPIO switches and have the output stored to a block in DDR3 memory when I press another switch. This is a totally useless function but basically I am trying to learn how to interface with the DDR3 block. I've already gone through UG406 and a bunch of other docments detailing how to use the MIG but it just generates a bunch of code in which I have no idea what's going on. I would basically like to know how to:


1) Create my own VHDL code and instantiate this DDR3 MIG block.

2) Interface with it.


I apologize for the very generic question but I guess I didn't look hard enough online for anything that could help me. I will appreciate your answers!



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Xilinx Employee
Xilinx Employee
Registered: ‎02-06-2013



Please refer below AR for the flow on how to include MIG in your design.


Refer UI read and write timing Diagrams in UG406 and you should be writing your own glue logic to drive the UI interface following the timing diagrams.



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Xilinx Employee
Xilinx Employee
Registered: ‎07-11-2011



You can simply use flow-1 of AR 37424, generate ISE priject, run example design simulation to undersatnd the flow and then comment out traffic gen in example_top.vhd and have your own fsm to interface user interface signals of the controller satisfying command path, write path and read path timing diagrams given in UG406


Hope this helps




Please do google search before posting, you may find relavant information.
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