cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
6,544 Views
Registered: ‎02-19-2016

Virtex 6 to a DAC

Hello again Xilinx Forums,

I'm a new user who's trying to configure the output of my fpga to the inputs on a dac. My particular fpga is the ml605 and the dac I'm using is the ad9129, both of which are meant to be compatible with each other and I have verified that both work. 

 

My question is how might I be able to set the port map of my VHDL script such that I can interface the two pieces of hardware? I already have simple DSP programs written in vhdl to test the two once I have them working together yet I don't even know how to start with connecting them. Also, I have both the UCF file for my specific board and the ucf file for the dac, it actually pertais to a board that connects the dac to the FMC-LPC connector. 

0 Kudos
2 Replies
Highlighted
Teacher
Teacher
6,470 Views
Registered: ‎03-31-2012

Re: Virtex 6 to a DAC

do you have this chip on a board with an FMC connector? If so, you need to find which pins are connected on the FMC to the DAC, and which FPGA pins are connected to the FMC connector's same pins. Then it's an easy mapping from the FPGA. If you want to drive say a signal D0 to the DAC, you need to instantiate an OBUFDS, connect internal D0 net to its input and the two outputs to the FPGA pins which are connected to the FMC connector which are routed to the DAC.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Highlighted
Visitor
Visitor
6,355 Views
Registered: ‎02-19-2016

Re: Virtex 6 to a DAC

Thank you for the response, but I'm still somewhat confused by this process as I've never set such a complex port map in VHDL before. 

 

Yes, I am interfacing my fpga directly to an FMC connector rather than the actual DAC an am attempting the connection using the UCF file for the FMC. Also, I'm not positive how I might instantiate the OBUFDS (which is a bundle of differential output signals?). Is there a guide online to shw me how the syntax might change when using OBUFDS?

 

Also I've found a section in the FMC UCF that seems to have instructions for what I'm looking for:

 

------------------------------------------------------------------------------
# "test design" specific constraints ( controllable sinewave )
# ------------------------------------------------------------------------------
NET "CLK_DCOA_P" TNM_NET = CLK_DCOA_P;
TIMESPEC TS_DCLK_DCOA_P = PERIOD "CLK_DCOA_P" 625 MHz HIGH 50%;
NET "CLK_DCOB_P" TNM_NET = CLK_DCOB_P;
TIMESPEC TS_DCLK_DCOB_P = PERIOD "CLK_DCOB_P" 625 MHz HIGH 50%;

# Must control the Dedicated Route for the clock not on GC pin...
#NET "CLK_DCOA_P" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "my_clks/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "CLK_DCOB_P" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "my_clks/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE;

# INST "TST_dac_if/SELECT_COMPLEX_MODEL.OSERDES_QBport/clkout_buf_inst" LOC = BUFR_X0Y0; # when used with DCOA
# INST "SELECT_SIMPLE_ODDR_MODEL.my_clks/mmcm_adv_inst" LOC = MMCM_ADV_X0Y0;
#...INST "SELECT_COMPLEX_MODEL.my_clks/mmcm_adv_inst" LOC = MMCM_ADV_X0Y0;
# INST "TST_dac_if/SELECT_COMPLEX_MODEL.OSERDES_QBport/clkout_buf_inst" LOC = BUFR_X0Y5; # when used with DCOB
# INST "my_clks/mmcm_adv_inst" LOC = MMCM_ADV_X0Y4;

INST "*BUFG*" TPTHRU = "GLOBAL_BUFFERS";
TIMESPEC TS_FROM_PADS_THRU_GLOBAL_BUFFERS = FROM PADS THRU "GLOBAL_BUFFERS" 5 ns;

#

 

Thanks for all the patience this must take,

Donald

0 Kudos