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Observer
Observer
7,018 Views
Registered: ‎11-13-2009

Virtex6 ML605 and GMII

Hi,

 

Since some time I'm trying to communicate with my ML605 via the ethernet connector. To get started I used the Ethernet MAC example with address switch from the Core Generator and managed to get it working for MII at 10/100Mbit/s. Encouraged by this I moved on to the GMII with 1000Mbit/s as I need this speed to send silicon sensor data (sensor will be connected via the FMC connector) to the PC.

But here I'm having some trouble to get it working (I should out that I have not much experience with FPGAs). What I did so far:

 

1. Generate the Ethernet MAC Core v1.5

2. Since there is no 125 MHZ reference clock on the board I "derived" (is this the correct term) it from the 200 MHZ differential clock on the board.

 

After that I generated the bit-file and programmed the FPGA, but the communication is not working. When I send a package the Receive-LED blinks up, but the package is not retransmitted to my PC again. My suspission is that I messed

up some timing constraints since I am not sure how to deal with the derived clock. I attached the project, so please, if anyone could give me some hints how to proceed I would be very pleased.

 

Cheers,

Tobias

 

PS: Sorry if made spelling errors I am not a native speaker

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7 Replies
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Explorer
Explorer
7,014 Views
Registered: ‎04-09-2008

2. Since there is no 125 MHZ reference clock on the board I "derived" (is this the correct term) it from the 200 MHZ differential clock on the board.

 

There is a low-jitter 125MHz reference clock connected to at least one pair of GTX reference clock pins.

 

When I send a package the Receive-LED blinks up, but the package is not retransmitted to my PC again.

 

There's a lot going on between the interface to your core and your Ethernet connected PC.  There could be problem(s) many places between, including but not limited to your constraints.  I would recommend you try using the Xilinx Embedded Developer's Kit (EDK) to get started with your design.  Once you've proven your concept with an embedded microprocessor, then shift to a lower-latency core generator based project.

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Observer
Observer
6,999 Views
Registered: ‎11-13-2009

Hi

Tanks for your reply. I was following this thread (http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Virtex6-ML605-and-GMII/td-p/232615) and there the solution was to create the 125 MHZ with the clock generator.

Could point out which pin to use on the fpga to get GTX reference clock pins. A great help would maybe be a working example for GMII on the ML605 evalboard. 

 

Cheers,

Tobi

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Observer
Observer
6,988 Views
Registered: ‎11-13-2009

Hi,

 

To add somethin more. For example starting from the generated files from the coregenerator and adding my top-file I get the following error when I try to compile:

 

Constraint <INST "bufg_tx" LOC = "BUFGCTRL_X0Y6";>
   [top.ucf(183)]: INST "bufg_tx" not found

 

Which I don't know you to solve this, because bufg_tx appears in ethernet_mac_example.vhd. And the same thing happens for refclk_bufg.

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Explorer
Explorer
6,983 Views
Registered: ‎04-09-2008

Try using  a wildcard ("*").

 

You should read the Xilinx Constraints User Guide.  It explains a lot about how the constraint system works, including how to specify the names of signals in your design.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ug612.pdf

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Observer
Observer
6,980 Views
Registered: ‎11-13-2009

Ok, thanks. Maybe I will come back after enyoing a good read.

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Observer
Observer
6,967 Views
Registered: ‎11-13-2009

Hi,

 

With your help and the maual you send me I was able to get rid of some warnings in the map-process connected to my timing constraints. All I had to do was using the timing groups generated due to the presence of the  clocks generated by the clock manager (see .ucf-file).

But the design is still not working. The receive-led lights up but nothing is transmitted to the pc by the eval-board (checked with wireshark). Do you have any suggestions what to do next? Unfortunately I can not use EDK because I have no license and my thesis supervisor will not buy one just because of this problem (I guess),

 

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Explorer
Explorer
6,959 Views
Registered: ‎04-09-2008

Do you have access to Chipscope?  You can use the Chipscope Core Inserter to synthesize a small logic analyzer in your FPGA, alongside the Ethernet example design you are testing.  After inserting the core, you connec to it using the Analyzer program via JTAG.  You can set triggers and watch the ports of the address swap module to determine how far the packets you send from your PC are making it.

 

Are you using GMII?  SGMII?  If you're having trouble with one, I would try the other.  SGMII should be easier to get working, since GMII might require some fine-tuning of the offset delays - probably using IODELAY logic.

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