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Visitor litaoyangxi
Visitor
9,087 Views
Registered: ‎04-22-2015

Vivado 2013.4 implementation critical warnings with Tri Mode Ethernet MAC IP on Zynq ZC702 Evaluation Board

Hello everybody!

 

I am working on a ZC702 board and  I received some critical warnings during the implementation flow with the example design of Tri Mode Ethernet MAC IP. All of these are concerning the .xdc file. I have not found any solution on the Internet concerning my situation.

 

The follow is the critial warnings.

 

[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["F:/.../tri_mode_ethernet_mac_0_example_design.xdc":44]

 

-> (Concerned lines)

 

set_property PACKAGE_PIN C12 [get_ports mdio]
set_property IOSTANDARD LVCMOS25 [get_ports mdio]

I checked zc702's user guide xtp185 and the pins' location is right.

 

Another kind of critical warnings are these ones :

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/inst/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i at A13 (IOPAD_X1Y103) since it belongs to a shape containing instance trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/inst/rgmii_interface/rxdata_in_bus[3].rgmii_rx_data_in. The shape requires relative placement between trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/inst/rgmii_interface/ibuf_data[3].rgmii_rxd_ibuf_i and trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/inst/rgmii_interface/rxdata_in_bus[3].rgmii_rx_data_in that cannnot be honored because it would result in an invalid location for trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/inst/rgmii_interface/rxdata_in_bus[3].rgmii_rx_data_in. ["F:/vivado/zync/tri_mode_ethernet_mac_0_example/tri_mode_ethernet_mac_0_example.srcs/constrs_1/imports/example_design/tri_mode_ethernet_mac_0_example_design.xdc":48]

-> (Concerned lines)

set_property PACKAGE_PIN A13 [get_ports rgmii_rxd[3]]
set_property IOSTANDARD HSTL_I_18 [get_ports {rgmii_rxd[3]}]

I use the pins designed by the ZC702's user guide ug850 and xtp185. All of this leads to this error during the BitStream generation :

[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 15 out of 25 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: rgmii_rxd[3:0], rgmii_txd[3:0], mdc, mdio, phy_resetn, rgmii_rx_ctl, rgmii_rxc, rgmii_tx_ctl, rgmii_txc.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

So where I am wrong?

 

Regards,

Luc

 

 

 

 

 

 

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3 Replies
Community Manager
Community Manager
9,073 Views
Registered: ‎06-14-2012

Re: Vivado 2013.4 implementation critical warnings with Tri Mode Ethernet MAC IP on Zynq ZC702 Evaluation Board

This seems valid. Is it possible to check in latest versions?

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Visitor litaoyangxi
Visitor
9,062 Views
Registered: ‎04-22-2015

Re: Vivado 2013.4 implementation critical warnings with Tri Mode Ethernet MAC IP on Zynq ZC702 Evaluation Board

I have also tried it with vivado 2014.1 and 2014.2, and the result was the same.

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Community Manager
Community Manager
9,026 Views
Registered: ‎06-14-2012

Re: Vivado 2013.4 implementation critical warnings with Tri Mode Ethernet MAC IP on Zynq ZC702 Evaluation Board

Have you added these pins? This seems dedicated for ZC702 boards.

 

Regards

Sikta

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