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Newbie mxu_xilinx
Newbie
83 Views
Registered: ‎06-15-2018

Vivado Failed Implmentation but without any error message

Hi

I got some problem and need soem help.

Whern I run implmenetation, it faild opt_dsign and said one error encounted. However, it does not have any error message.  It is very consistant.  I could not pass this stage.

For this project, I am still using Vivado version 2015.4

Can anyone help to point out what is wrong and how can I find the error message?

 

Thanks

Ming

 

Below is the message:


Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.451 . Memory (MB): peak = 1187.012 ; gain = 0.000
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'VIRTUAL_clkout0' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/Projects/Fortress_Header/PE_FPGA/opal_pe_firmware/xdc/system.xdc:253]
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'VIRTUAL_clkout1' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/Projects/Fortress_Header/PE_FPGA/opal_pe_firmware/xdc/system.xdc:254]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task
INFO: [Common 17-83] Releasing license: Implementation
82 Infos, 265 Warnings, 220 Critical Warnings and 1 Errors encountered.
opt_design failed
INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 10:26:51 2019...

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