What is the maximum supported CONFIGRATE value for VCU128 EVB ??

[wangxiao@skhms]

Hi Xilinx Support,

When creating the MCS file for programming the VCU128 EVB boot flash memory, what is the maximum CONFIGRATE value allowed for user to use? I searched the VCU128 related documents and could not find out this number. It is not practical to try it out by varying the number in lab.  The VCU128 EVB has a pre-loaded bit-file in the boot flash memory, what is the CONFIGRATE value used in that bitfile?

Thanks,

Xiao

[markg@prosensing.com]

wangxiao@skhms 

CONFIGRATE planning for the Virtex UltraScale+ on the VCU128 board starts by noting from UG1302 that configuration from flash uses the Master SPI mode and the internal CCLK.  

From the Virtex UltraScale+ datasheet (DS923) we find that the maximum frequency, FMCCK_MAX, for CCLK is 125MHz.  However, the tolerance, FMCCKTOL, of the CCLK generator is 15%.  Hence, we cannot specify a CCLK frequency faster than (125/1.15)=108MHz. 

Other calculations shown on pages 54-55 of UG570 (v1.11) can reduce the allowed CCLK frequency further. 

Finally, only discrete values of the CCLK frequency are available and these are shown to you by Vivado when you open the implemented design and select Settings > Bitstream > Configure-additional-bistream-settings > Configuration > Configuration Rate (MHz).

[wangxiao@skhms]

Thanks for the input, but I still do not get what is the best number for the CONFIGRATE used for VCU128.

Like you pointed out that there are about 14 selecting options in the "conficuration rate" menu, I would like to know which number is selected by Xilinx for building their demo bitfile of "blinkbist.bit" (see rdf0494-vcu128-restoring-flash-c-2019-1) preloaded in the VCU128 boot flash. Xilinx should provide this number in the VCU128 users guide, instead of asking user to try it out in lab. 

Thanks.

Xiao

[hj]

You can follow the XAPP https://www.xilinx.com/support/documentation/application_notes/xapp1233-spi-config-ultrascale.pdf {page#30-31}to find the max configuration rate.
Maximum value for this board would be 67.34 Mhz (including +/-35% CCLK tolerance).
Possible nearest value for max configuration rate is 63.8 Mhz. I believe it would be set for this value.

You can find the max value by following the XAPP. If higher value are needed then you can always have an option to go for EMCCLK. (External Master Configuration Clock)

Hope it helps.

Thanks
Harshit

[wangxiao@skhms · Accepted solution]

Thanks! This is exactly the one I am looking for, it will save me lots of time to try it out in lab.

Thank you very much for your help.

Xiao