cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
zengqh
Adventurer
Adventurer
879 Views
Registered: ‎01-10-2019

What's IO Standard of system clk300MHz with VCU108 Evaluttion Board?

Jump to solution

When I create a MMCM and use sysclk1 300M of VCU108 in input,and

E6(6PH@2`116EMH8`G54QQH.png

It will create default constrains use in synthesis and implement.So I direct run synthesis and implement,and see the IO Standard of sysclk1 300M is LVDS and use G31 port.HFLMCW)O@]}$74BA_$QFLN5.png

 

But I read ug1066 VCU108 Evalution Board User Guide and show IO Standard of sysclk1 300M in G31 is DIFF_SSTL12.H7VX(VU2ZI6PP1LV5}Z97BA.png

 

So I try changed my implement constrains,changed IO Standard to DIFF_SSTL12,but it created waning.W8_2MV3P`1D]{R}CC}~FHBC.png

 

So,What's IO Standard of system clk300MHz with VCU108 Evaluttion Board?And what should I do?

0 Kudos
1 Solution

Accepted Solutions
622 Views
Registered: ‎01-22-2015

@zengqh 

I think you should place the DIFF_SSTL12 constraints in Top_Imple.xdc and ignore the XDCC-2 warnings from “Report Methodology”.

You can check that Vivado implementation is using the DIFF_SSTL12 clock-input constraints (and not the clock-input constraints from the board files) by opening the implemented design and typing the following Tcl command in the Vivado Tcl Console.

write_xdc c:/temp/used_constraints.txt

write_xdc.jpg

The write_xdc command will create a file called “used_constraints.txt” in directory, c:/temp/, on your computer.  This file will contain all the constraints that were actually used during implementation. 

Instead of using the write_xdc command, you can also look at the “IO Ports” tab after opening the implemented design to see if the clock input ports have the DIFF_SSTL12 IO standard.

View solution in original post

8 Replies
828 Views
Registered: ‎01-22-2015

@zengqh 

To answer your questions, we can start by looking at the circuit that delivers “System clock 300 MHz”, SYSCLK1_300, to the FPGA, XCVU095-2FFVA2104E, of the VCU108 board.  This circuit is shown by the schematic below from Figure 1-9 of UG1066(v1.5).
SYSCLK1_300.jpg

Page 40 of UG1066 shows that SYSCLK1_300 is buffered by a SI53340-B-GN quad clock buffer, U157.  Output of the buffer goes to GC pins G31 and F31 which are in HP-bank 50 of the FPGA. 

Table 1-3 of UG1066 shows that VCCO for HP-bank 50 comes from power rail VCC1V2_FPGA, which is normally 1.2V.  The VCCO for the HP-bank 50 is also called VCCO_50.

Table 1-77 in UG571(v1.12) shows VCCO requirements for LVDS and for DIFF_SSTL12.  A voltage of 1.8V is preferred for LVDS and a voltage of 1.2V is preferred for DIFF_SSTL12  (see also footnotes (1) and (2) in this table about other values of VCCO).

So, based on a VCCO_50=1.2V, it seems that input to GC pins G31 and F31 should be DIFF_SSTL12.  Next, let’s check the specifications for DIFF_SSTL12.

Table 14 of the Virtex UltraScale datasheet, DS893(v1.12), gives DIFF_SSTL12 specifications for HP banks as follows:

  • input common mode voltage, VICM=(VCCO/2)+/-0.15V,
  • input differential voltage, VID=0.10V(min). 

Since VID(max) is not given, we can assume any VID(max) that satisfies the recommended operating conditions, (-0.20 to VCCO+0.20), for VIN shown in Table 2 of DS893.

Table 3.4 of the datasheet for SiLabs SI53340-B-GM shows that the differential output voltage (=2*VSE) ranges between 400-980mV.  In the above schematic from Figure 1-9 of UG1066, the AC-coupling and DC-biasing circuit consisting of (C650, C651, R594-R597) will give a common-mode voltage of VCC1V2_FPGA/2=VCCO_50/2.

So, circuits on the VCU108 board are delivering SYSCLK1_300 to pins G31 and F31 of the FPGA with voltages that *usually* satisfy DIFF_SSTL12 specifications for HP banks.  I say *usually* because at the high end, the SI53340-B-GM could deliver (VCCO_50/2)+980mV=1.58V to the FPGA pins.  This is higher than the recommended operating condition of VCCO_50+0.2=1.4V but not higher than the absolute maximum of VCCO_50+0.55=1.75V shown in Table 1 of DS893.

Finally, the XDC constraints file for the VCU108 shows the following constraints:

set_property PACKAGE_PIN G31      [get_ports "SYSCLK1_300_P"] ;# Bank  50 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_50
set_property IOSTANDARD  DIFF_SSTL12 [get_ports "SYSCLK1_300_P"] ;# Bank  50 VCCO - VCC1V2_FPGA - IO_L13P_T2L_N0_GC_QBC_50
set_property PACKAGE_PIN F31      [get_ports "SYSCLK1_300_N"] ;# Bank  50 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_50
set_property IOSTANDARD  DIFF_SSTL12 [get_ports "SYSCLK1_300_N"] ;# Bank  50 VCCO - VCC1V2_FPGA - IO_L13N_T2L_N1_GC_QBC_50

 

So, if you are using this constraints file in your project, then the FPGA pins G31 and F31 that receive SYSCLK1_300 are being configured correctly.

Cheers,
Mark

zengqh
Adventurer
Adventurer
767 Views
Registered: ‎01-10-2019

 markg@prosensing.com 

Thank you very much for your sincere answer!
Yes,I know I should use what IO Standard for G31 now.Finally,I also changed my constraints as you,but I also got same XDCC warning to upon, and that meaning I can ignore this warning and none to do?
Cheers!

0 Kudos
simon
Xilinx Employee
Xilinx Employee
751 Views
Registered: ‎08-25-2010

Hi @zengqh 

You can check if this clock constraints are included in the clk_sys_board.xdc. If so, you don't have to constrain it in your top_Impl.xdc.

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
zengqh
Adventurer
Adventurer
718 Views
Registered: ‎01-10-2019
@simon
yes,this clock constraints are included in the clk_sys_board.xdc,but the IO Standard is LVDS not DIFF_SSTL12,that meaning I can ignore this warning and none to do?
0 Kudos
simon
Xilinx Employee
Xilinx Employee
685 Views
Registered: ‎08-25-2010

Hi @zengqh 

No, you need to remove your constraints in top_impl.xdc.

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
zengqh
Adventurer
Adventurer
672 Views
Registered: ‎01-10-2019

Thank you very much for your sincere answers.@simon

I removed my constraints in top_impl.xdc,but G31 IO Standard changed LVDS,not DIFF_SSTL12 in ug157.This is my questions and confused.

0 Kudos
623 Views
Registered: ‎01-22-2015

@zengqh 

I think you should place the DIFF_SSTL12 constraints in Top_Imple.xdc and ignore the XDCC-2 warnings from “Report Methodology”.

You can check that Vivado implementation is using the DIFF_SSTL12 clock-input constraints (and not the clock-input constraints from the board files) by opening the implemented design and typing the following Tcl command in the Vivado Tcl Console.

write_xdc c:/temp/used_constraints.txt

write_xdc.jpg

The write_xdc command will create a file called “used_constraints.txt” in directory, c:/temp/, on your computer.  This file will contain all the constraints that were actually used during implementation. 

Instead of using the write_xdc command, you can also look at the “IO Ports” tab after opening the implemented design to see if the clock input ports have the DIFF_SSTL12 IO standard.

View solution in original post

zengqh
Adventurer
Adventurer
605 Views
Registered: ‎01-10-2019
Thank you very much for your sincere answer! .@markg@prosensing.com
I think you are right .
0 Kudos