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Observer
Observer
8,967 Views
Registered: ‎12-04-2013

Xilinx ZC702 Board PCB Trace Impedances

Hello everyone,

 

at the moment we are designing our own Board with Zynq XC7Z020-1.

 

We use Ethernet (PS, RGMII)  for which we need 50 Ohm single-ended and 100 Ohm differential impedance.

On the other hand we want to use DDR3-SDRAM with 533 MHz on the same board which needs 40 Ohm single-ended and 100 Ohm differential trace impedances.

 

Refering to Zedboard, there is a point in the errate document which says "ZedBoard DDR3 Single-Ended Trace Impedance Does Not Match UG933 Recommendation" and this is an accepted point because the memory is tested and works. Every Impedance-Checked parts are routed in a 50 Ohm single-ended topology.

 

What trace impedances are used on the XIlinx ZC702 Board?
Did Xilinx achieve to match the correct impedance for both Ethernet and DDR3?

 

Regards,

tk

 

 

 

 

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Xilinx Employee
Xilinx Employee
8,956 Views
Registered: ‎07-31-2012

Hi,

 

Please check the ZC702 schematics which show a parallel termination of 80.6ohm using the DCI resistance PS_VRP and PS_VRN. Check Pg 9 of the - link. These are pointing to the DDR3 signals as given in pg no 16. However these have been decided based on the board conditions and through simulations.

 

vrp.PNG

Similarly check for the RGMII termination in the schematic.

 

 

 

Thanks,
Anirudh

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Observer
Observer
8,951 Views
Registered: ‎12-04-2013

Thanks for your answer, Anirudh.

 

I knew before that the values of the components (Termination, DCI) fit to a 40 Ohm Implementation of DDR3-SDRAM.

 

I'm interested in the trace impedance for which the PCB is designed. Are the DDR3 tracks of ZC702 routed with 40 Ohm or 50 Ohm Impedance (single-ended)?

 

Zedboard uses 40 Ohm Termination and 50 Ohm traces. It seems to me like the HW Designers did this because they gave the specifications of ehernet a higher priority than DDR3 and its not possible to meet the requirements of both.

 

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Xilinx Employee
Xilinx Employee
8,935 Views
Registered: ‎01-03-2008

Boards are not forced to be designed with a single trace impedence.  The trace impedence is easily controlled with by selecting an appropriate width based on the dielectric constant of the material and the height from the reference plane. 

 

In the case of the ZC702 board the DDR3 data lines are routed as 40ohms with a 4.75mil width and the RGMII interface as 50ohms with a 4.25mil width.

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