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Observer
Observer
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Registered: ‎06-21-2017

ZC706 GPIO headers LVCMOS25

Dear all,

I am working with ZC706 and I configured GPIO headers J58 in order to operate two external signals. All pins of  the J58 connector are defined by xilinx under LVCMOS25. My pulsed external signals have 3.25V of amplitude. I am wondering if could it be possible to define this J58 connector as LVCMOS33 in the constranins file

Thanks

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @carloscruz

 

J58 pins i.e PMOD1_[0:7] are connected to the  TI TXS0108E 3.3V-to-VADJ level-shifter (U40) on the ZC706 board.

VADJ is 2.5V (Default).

 

temp.PNG

The level shifted signals i.e PMOD1_[0:7]_LS are routed to Bank 9, 10 & 11 powered by 2.5V (VADJ_FPGA).

Hence the IOSTANDRAD is LVCMOS25.

There will not be any problem by connecting external signal of amplitude 3.25V to the PMOD inputs as  level shifted (2.5V) signals are input to the FPGA banks.

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Observer
Observer
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Registered: ‎06-21-2017

thank you for your response. Do you mean that I can connect a 3.2V signal to PMOD and the constraints are defined, for example, as followed:  set_property PACKAGE_PIN AC19 [get_ports PMOD1_7_LS]

                set_property IOSTANDARD LVCMOS25 [get_ports PMOD1_7_LS]

 

Does this pin need to be configured as LVCMOS33 if the signal is 3.2V?

thanks

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Moderator
Moderator
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Registered: ‎08-08-2017

Hi @carloscruz

 

The constraints are correct . Though the Amplitude of External Signal is 3.2V, but it is level shifted to 2.5V (Output from

TI TXS0108E  i.e U40 in the schematic)

 

Input to the FPGA  is Level shifted signal i.e PMOD1_7_LS of amplitude 2.5V not the 3.2V signal.

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