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Registered: ‎06-16-2016

ZCU-102 board SFP 0 gt_ref_clk issue

HI all ,

I'm using ZCU-102 board for XGMII . right now I'm using example design for that I tried to use R9/R10 pins as given in user guide (ug1182) of board but its showing error like at bit stream. so 

  • [DRC UCIO-1] Unconstrained Logical Port: 2 out of 16 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gt_refclk_p, and gt_refclk_n.

    so what is solution for this . is there any another pin's if it there pls let me know. 

    pls reply ASAP.

    thank you.
    Lalith kumar
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Registered: ‎06-05-2013

Re: ZCU-102 board SFP 0 gt_ref_clk issue

Have you added the following LOC constraints in the design xdc? If not then please add them.


set_property PACKAGE_PIN R9 [get_ports "SFP_REC_CLOCK_C_N"]

set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_N"]

set_property PACKAGE_PIN R10 [get_ports "SFP_REC_CLOCK_C_P"]

set_property IOSTANDARD LVDS [get_ports "SFP_REC_CLOCK_C_P"]


If you have already added them then check this Xilinx AR 56354


Don’t forget to reply, kudo, and accept as solution.
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