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Visitor pg_r
Visitor
181 Views
Registered: ‎04-02-2019

ZCU102 AXI Access From Top VHDL module

Hello,

The wrapper generated from .bd shows external ports (going out of the FPGA).

I have a module created interfacing with PORT B of a Dual Port RAM (instantiated as an IP to the ram controller) and the other side is connected to Zynq PS (PORT A).

Now I want to bring some registers from my local module to the wrapper so that I can use the memory data with other VHDL modules, what's the best way to accomplish that?

 Please advise

Thanks

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1 Reply
Xilinx Employee
Xilinx Employee
133 Views
Registered: ‎06-21-2018

Re: ZCU102 AXI Access From Top VHDL module

Hi pg_r,

Not sure what I fully understand your use case, but I would start by taking a look at UG1209:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1209-embedded-design-tutorial.pdf

In particular, take a look at the Design Example 1. On page 135 it shows how to add AXI interfaces to your Block Diagram and create a wrapper with them.

Thanks,
Andres

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