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Contributor
Contributor
2,215 Views
Registered: ‎03-20-2018

ZCU102 Board Interface Test Failures

I'm running the BIT test suite on a new ZCU102 after setting it up according to xtp435. Unfortunately I'm getting failures on these tests:

  • ZCU102 RTC
  • MIG PS DDR4
  • MIG PL DDR4
  • PING
  • UART 01/02 Test
  • IPI Test

 

The IP for my Ethernet connection has been set to 192.168.1.2 per xtp435.

Both USB Connections are in place.

I can talk to the board using the Hardware Manager, although all I see is the temperature monitors

 

I've attached a log of the complete BIT suite run and a screen shot of the BIT application after running the test suite.BIT Failure Screen.png

0 Kudos
23 Replies
Xilinx Employee
Xilinx Employee
2,070 Views
Registered: ‎03-07-2018

Re: ZCU102 Board Interface Test Failures

Hi barrygmoss,

 

 

for Error: 'comm' type in step 0 never found a serial port to connect to in test 2

 

Cause of this error is UART connection problem it can be resolved with method suggested in AR#68521

 

and also check https://forums.xilinx.com/t5/Welcome-Join/VCU118-developmental-board-fails-the-VCU118-setup-test-in-XTP439/td-p/763828

 

Regards,

Bhushan

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Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
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0 Kudos
Contributor
Contributor
2,034 Views
Registered: ‎03-20-2018

Re: ZCU102 Board Interface Test Failures

My COM ports were showing as CP2108, so I updated the config.json file per AR#68521, but this didn't make any difference to the operation of BIT and SCUI showed no change either (although it was already working). 

 

SI Labs Ports.png

 

My system is using the 10.1.1.1951 drivers under Windows Pro 10.0.16299.309. Per https://forums.xilinx.com/t5/Welcome-Join/VCU118-developmental-board-fails-the-VCU118-setup-test-in-XTP439/td-p/763828 I tried to find the recommended 6.7.1 driver from https://www.silabs.com/products/development-tools/software/usb-to-uart-bridge-vcp-drivers but that version is no longer available and the site offers 10.1.1 and 6.7.5 only. 6.7 is listed but does not support Windows 10. 

 

I'm still getting the "Error: 'comm' type in step 0 never found a serial port to connect to in test 2" error in the RTC test (as well as the other errors noted previously). 

 

 

0 Kudos
Participant mnanoop2014
Participant
1,644 Views
Registered: ‎10-29-2018

Re: ZCU102 Board Interface Test Failures

Hi
For the RTC test, there is a solution.

As per Andrew's comments for the System controller GUI/Firmware update which is discussed here:

link

 

You can try and open the default.json and default.json.bak files with notepad and changing the following line in both of them:

"port": "Silicon Labs Quad CP210x USB to UART Bridge: Interface 0",

to

"port": "Silicon Labs Quad CP2108 USB to UART Bridge: Interface 0",

or whichever number pops up in your device manager com port info.

0 Kudos
Participant mnanoop2014
Participant
1,638 Views
Registered: ‎10-29-2018

Re: ZCU102 Board Interface Test Failures

And also, for the ethernet/PING test, you can edit the IP address of the board in the same two files along with changing the IP address in the PING batch file in one of the accompanying folders. 

0 Kudos
Xilinx Employee
Xilinx Employee
1,624 Views
Registered: ‎06-13-2018

Re: ZCU102 Board Interface Test Failures

Hello @barrygmoss,

 

 

Are you using Non-English Operating System? The reason for asking this question is that When you are running the Board Interface test (XTP428) on a ZCU102 board, the PING test might fail if using a non-English OS. For more details Please follow AR-69745.

 

Regards,

Naveen

 

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0 Kudos
1,127 Views
Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

I am using Windows 10, Vivado 2019.1, and Silicon Labs Driver v10.1.8

ZCU102 IDCODE Check, ZCU102 SETUP, PMBUS TEST and MIG PL DDR4 pass.

ZCU102 RTC, MIG PS DDR4, PING, UART 01/02 TEST and IPI Test fail.

I tried chainging CP210x to CP2018 (as shown in device manager) in the defaults.json and defaults.json.bak files, however I still get "Error: 'comm' type in step 0 never found a serial port to connect to in test 2" in the ZCU102  RTC test.

Help is apreciated, thanks.

Below are the logs for the all failures:

 

Info: ZCU102 RTC test started...

Info: The test will take 0 hours, 00 minutes, and 38 seconds. 0:00:38

Info: This step started at: 2019-06-28 11:45:59

step finished

Error: 'comm' type in step 0 never found a serial port to connect to in test 2

Info: This step started at: 2019-06-28 11:45:59

Error: Stopped because step 0 failed in test 2

Info: Result for step 0: Fail
Info: The test took 0 hours, 00 minutes, and 00 seconds. 0:00:00

Info: MIG PS DDR4 test started...

Info: The test will take 0 hours, 00 minutes, and 38 seconds. 0:00:38

Info: This step started at: 2019-06-28 11:57:25

Info: This step started at: 2019-06-28 11:57:25

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}

rst -system

after 1000

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init

after 1000

psu_ps_pl_isolation_removal

after 1000

psu_ps_pl_reset_config

targets -set -filter {name =~"*A53*0"}

rst -processor

after 1000

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/zynq_mp_dram_test.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/zynq_mp_dram_test.elf
section, .text: 0xfffc0000 - 0xfffdcd7b
section, .boot: 0xffff0000 - 0xffff0b8f
section, .init: 0xffff0bc0 - 0xffff0bf3
section, .fini: 0xffff0c00 - 0xffff0c33
section, .note.gnu.build-id: 0xfffdcd7c - 0xfffdcd9f
section, .rodata: 0xfffdcda0 - 0xfffdf707
section, .rodata1: 0xfffdf708 - 0xfffdf73f
section, .sdata2: 0xfffdf740 - 0xfffdf73f
section, .sbss2: 0xfffdf740 - 0xfffdf73f
section, .data: 0xfffdf740 - 0xfffe12ef
section, .data1: 0xfffe12f0 - 0xfffe12ff
section, .ctors: 0xfffe1300 - 0xfffe12ff
section, .dtors: 0xfffe1300 - 0xfffe12ff
section, .eh_frame: 0xfffe1300 - 0xfffe1303
section, .mmu_tbl0: 0xfffe2000 - 0xfffe200f
section, .mmu_tbl1: 0xfffe3000 - 0xfffe4fff
section, .mmu_tbl2: 0xfffe5000 - 0xfffe8fff
section, .preinit_array: 0xfffe9000 - 0xfffe8fff
section, .init_array: 0xfffe9000 - 0xfffe9007
section, .fini_array: 0xfffe9008 - 0xfffe9047
section, .sdata: 0xfffe9048 - 0xfffe907f
section, .sbss: 0xfffe9080 - 0xfffe907f
section, .tdata: 0xfffe9080 - 0xfffe907f
section, .tbss: 0xfffe9080 - 0xfffe907f
section, .bss: 0xfffe9080 - 0xfffea63f
section, .heap: 0xffff0c34 - 0xffff2c3f
section, .stack: 0xffff2c40 - 0xffff5c3f

0% 0MB 0.0MB/s ??:?? ETA
67% 0MB 0.2MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0xffff0000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/zynq_mp_dram_test.elf

targets -set -filter {name =~"*A53*0"}

con

after 2000

********************************************************************************
Zynq MPSoC
DRAM Diagnostics Test (A53)
********************************************************************************
Select one of the options below:

+--------------------------------------------------------------------+
| Memory Tests |

+-----+--------------------------------------------------------------+
| '0' | Test first 2MB region of DDR |

| '1' | Test first 32MB region of DDR |

| '2' | Test first 64MB region of DDR |

| '3' | Test first 128MB region of DDR |

| '4' | Test first 256MB region of DDR |

| '5' | Test first 512MB region of DDR |

| '6' | Test first 1GB region of DDR |

| '7' | Test first 2GB region of DDR |

| '8' | Test first 4GB region of DDR |

| '9' | Test first 8GB region of DDR |

+-----+--------------------------------------------------------------+
| Eye Tests |

+-----+--------------------------------------------------------------+
| 'r' | Perform a read eye analysis test |
| 'w' | Perform a write eye analysis test |
| 'a' | Print test start address |
| 't' | Specify test start address (default=0x0) |
| 's' | Select the DRAM rank (default=1) |
+-----+--------------------------------------------------------------+
| Miscellaneous options |
+-----+--------------------------------------------------------------+
| 'i' | Print DDR information |
| 'v' | Verbose Mode ON/OFF |
| 'o' | Toggle cache enable/disable |
| 'b' | Toggle between 32/64-bit bus widths |
| 'h' | Print this help menu |
+-----+--------------------------------------------------------------+
Bus Width = 64, D-cache is enable, Verbose Mode is OFF

DDR ECC is DISABLED
Enter 'h' to print help menu
Enter Test Option:

disconnect

step finished

Info: This step started at: 2019-06-28 11:57:40
Writing: '2\n'
2

Starting Memory Test '2' - Testing 64MB length from address 0x0...

---------+--------+------------------------------------------------+-----------
TEST | ERROR | PER-BYTE-LANE ERROR COUNT | TIME
| COUNT | LANES [ #0, #1, #2, #3, #4, #5, #6, #7] | (sec)
---------+--------+------------------------------------------------+-----------

step finished

Error: Could not find regular expression in step 0 of test 4 - "(.*)memtest_all:\s+PASSED"

Error: Could not find regular expression in step 0 of test 4 - "(.*)error_counter\s+=\s+0x0000000000000000"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Fail

Info: The test took 0 hours, 00 minutes, and 36 seconds. 0:00:36

Info: UART 01/02 TEST test started...

Info: The test will take 0 hours, 00 minutes, and 52 seconds. 0:00:52

Info: This step started at: 2019-06-28 11:58:23

Info: This step started at: 2019-06-28 11:58:23

Info: This step started at: 2019-06-28 11:58:23

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}

rst -srst


fpga -state
FPGA is not configured

targets -set -filter {name =~"*APU*"}

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init

after 1000

psu_ps_pl_isolation_removal

after 1000

psu_ps_pl_reset_config

catch { psu_protection }
0
targets -set -filter {name =~"*A53*0"}

rst -processor

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/hello_uart_1.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_uart_1.elf
section, .text: 0x00000000 - 0x00002753
section, .init: 0x00002780 - 0x000027b3
section, .fini: 0x000027c0 - 0x000027f3
section, .note.gnu.build-id: 0x000027f4 - 0x00002817
section, .rodata: 0x00002818 - 0x00002a77
section, .rodata1: 0x00002a78 - 0x00002a7f
section, .sdata2: 0x00002a80 - 0x00002a7f
section, .sbss2: 0x00002a80 - 0x00002a7f
section, .data: 0x00002a80 - 0x00003367
section, .data1: 0x00003368 - 0x0000337f
section, .ctors: 0x00003380 - 0x0000337f
section, .dtors: 0x00003380 - 0x0000337f
section, .eh_frame: 0x00003380 - 0x00003383
section, .mmu_tbl0: 0x00004000 - 0x0000400f
section, .mmu_tbl1: 0x00005000 - 0x00006fff
section, .mmu_tbl2: 0x00007000 - 0x0000afff
section, .preinit_array: 0x0000b000 - 0x0000afff
section, .init_array: 0x0000b000 - 0x0000b007
section, .fini_array: 0x0000b008 - 0x0000b047
section, .sdata: 0x0000b048 - 0x0000b07f
section, .sbss: 0x0000b080 - 0x0000b07f
section, .tdata: 0x0000b080 - 0x0000b07f
section, .tbss: 0x0000b080 - 0x0000b07f
section, .bss: 0x0000b080 - 0x0000b0bf
section, .heap: 0x0000b0c0 - 0x0000d0bf
section, .stack: 0x0000d0c0 - 0x000100bf

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_uart_1.elf

targets -set -filter {name =~"*A53*0"}

con

after 2000

disconnect

step finished

Info: This step started at: 2019-06-28 11:58:38

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}

rst -srst


fpga -state
FPGA is not configured

fpga -file {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../bitstream/zcu102_ipi.bit}

initializing
0% 0MB 0.0MB/s ??:?? ETA
4% 1MB 2.2MB/s ??:?? ETA
7% 1MB 1.9MB/s ??:?? ETA
10% 2MB 1.8MB/s ??:?? ETA
14% 3MB 1.8MB/s ??:?? ETA
17% 4MB 1.7MB/s ??:?? ETA
21% 5MB 1.7MB/s 00:11 ETA
24% 6MB 1.7MB/s 00:11 ETA
28% 7MB 1.7MB/s 00:10 ETA
32% 8MB 1.7MB/s 00:09 ETA
35% 9MB 1.7MB/s 00:09 ETA
39% 9MB 1.7MB/s 00:09 ETA
43% 10MB 1.7MB/s 00:08 ETA
46% 11MB 1.7MB/s 00:07 ETA
49% 12MB 1.7MB/s 00:07 ETA
52% 13MB 1.7MB/s 00:07 ETA
56% 14MB 1.7MB/s 00:06 ETA
60% 15MB 1.7MB/s 00:05 ETA
63% 16MB 1.7MB/s 00:05 ETA
67% 17MB 1.7MB/s 00:04 ETA
71% 18MB 1.7MB/s 00:04 ETA
74% 18MB 1.7MB/s 00:03 ETA
78% 19MB 1.7MB/s 00:03 ETA
82% 20MB 1.7MB/s 00:02 ETA
86% 21MB 1.7MB/s 00:02 ETA
90% 22MB 1.7MB/s 00:01 ETA
94% 23MB 1.7MB/s 00:00 ETA
97% 24MB 1.7MB/s 00:00 ETA
100% 25MB 1.7MB/s 00:14

fpga -ir-status
IR STATUS: 117
Always One (Bits [0]): 1
Always Zero (Bits [1]): 0
ISC_Done (Bits [2]): 1
ISC_Enabled (Bits [3]): 0
Init Complete (Bits [4]): 1
DONE (Bits [5]): 1
(Bits [11:6]): 1
targets -set -filter {name =~"*APU*"}

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init

after 1000

psu_ps_pl_isolation_removal

after 1000

psu_ps_pl_reset_config

catch { psu_protection }
0
targets -set -filter {name =~"*A53*0"}

rst -processor

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/hello_uart_2.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_uart_2.elf
section, .text: 0x00000000 - 0x00002693
section, .init: 0x000026c0 - 0x000026f3
section, .fini: 0x00002700 - 0x00002733
section, .note.gnu.build-id: 0x00002734 - 0x00002757
section, .rodata: 0x00002758 - 0x000029b7
section, .rodata1: 0x000029b8 - 0x000029bf
section, .sdata2: 0x000029c0 - 0x000029bf
section, .sbss2: 0x000029c0 - 0x000029bf
section, .data: 0x000029c0 - 0x000032a7
section, .data1: 0x000032a8 - 0x000032bf
section, .ctors: 0x000032c0 - 0x000032bf
section, .dtors: 0x000032c0 - 0x000032bf
section, .eh_frame: 0x000032c0 - 0x000032c3
section, .mmu_tbl0: 0x00004000 - 0x0000400f
section, .mmu_tbl1: 0x00005000 - 0x00006fff
section, .mmu_tbl2: 0x00007000 - 0x0000afff
section, .preinit_array: 0x0000b000 - 0x0000afff
section, .init_array: 0x0000b000 - 0x0000b007
section, .fini_array: 0x0000b008 - 0x0000b047
section, .sdata: 0x0000b048 - 0x0000b07f
section, .sbss: 0x0000b080 - 0x0000b07f
section, .tdata: 0x0000b080 - 0x0000b07f
section, .tbss: 0x0000b080 - 0x0000b07f
section, .bss: 0x0000b080 - 0x0000b0bf
section, .heap: 0x0000b0c0 - 0x0000d0bf
section, .stack: 0x0000d0c0 - 0x000100bf

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_uart_2.elf

targets -set -filter {name =~"*A53*0"}

con

after 2000

disconnect

step finished

step finished

Error: Could not find regular expression in step 0 of test 7 - "(.*)UART\s+01\s+Test\s+Passed"

Info: Result for step 0: Fail
step finished

Error: Could not find regular expression in step 1 of test 7 - "(.*)UART\s+02\s+Test\s+Passed"

Info: Result for step 1: Fail
Info: Result for step 2: Pass
Info: Result for step 3: Pass

Info: The test took 0 hours, 00 minutes, and 48 seconds. 0:00:48

Info: IPI Test test started...

Info: The test will take 0 hours, 01 minutes, and 09 seconds. 0:01:09

Info: This step started at: 2019-06-28 11:59:17

Info: This step started at: 2019-06-28 11:59:18

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}


rst -srst

fpga -state
FPGA is not configured

fpga -file {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../bitstream/zcu102_ipi.bit}

initializing
0% 0MB 0.0MB/s ??:?? ETA
4% 1MB 2.1MB/s ??:?? ETA
7% 1MB 1.9MB/s ??:?? ETA
10% 2MB 1.8MB/s ??:?? ETA
14% 3MB 1.8MB/s ??:?? ETA
17% 4MB 1.7MB/s ??:?? ETA
21% 5MB 1.7MB/s 00:11 ETA
24% 6MB 1.7MB/s 00:11 ETA
28% 7MB 1.7MB/s 00:10 ETA
32% 8MB 1.7MB/s 00:10 ETA
35% 8MB 1.7MB/s 00:09 ETA
39% 9MB 1.7MB/s 00:09 ETA
43% 10MB 1.7MB/s 00:08 ETA
46% 11MB 1.7MB/s 00:07 ETA
50% 12MB 1.7MB/s 00:07 ETA
53% 13MB 1.7MB/s 00:06 ETA
57% 14MB 1.7MB/s 00:06 ETA
61% 15MB 1.7MB/s 00:05 ETA
64% 16MB 1.7MB/s 00:05 ETA
68% 17MB 1.7MB/s 00:04 ETA
72% 18MB 1.7MB/s 00:04 ETA
75% 19MB 1.7MB/s 00:03 ETA
79% 20MB 1.7MB/s 00:03 ETA
82% 20MB 1.7MB/s 00:02 ETA
86% 21MB 1.7MB/s 00:02 ETA
89% 22MB 1.7MB/s 00:01 ETA
93% 23MB 1.7MB/s 00:01 ETA
96% 24MB 1.7MB/s 00:00 ETA
100% 25MB 1.7MB/s 00:14

fpga -ir-status
IR STATUS: 117
Always One (Bits [0]): 1
Always Zero (Bits [1]): 0
ISC_Done (Bits [2]): 1
ISC_Enabled (Bits [3]): 0
Init Complete (Bits [4]): 1
DONE (Bits [5]): 1
(Bits [11:6]): 1
fpga -state
FPGA is configured

targets -set -filter {name =~"*APU*"}

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init


psu_ps_pl_isolation_removal


psu_ps_pl_reset_config

catch { psu_protection }
0
targets -set -filter {name =~"*A53*0"}

rst -processor

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/ipi_app_basic.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/ipi_app_basic.elf
section, .text: 0x00000000 - 0x00020a77
section, .init: 0x00020a80 - 0x00020ab3
section, .fini: 0x00020ac0 - 0x00020af3
section, .note.gnu.build-id: 0x00020af4 - 0x00020b17
section, .rodata: 0x00020b18 - 0x00024e57
section, .rodata1: 0x00024e58 - 0x00024e7f
section, .sdata2: 0x00024e80 - 0x00024e7f
section, .sbss2: 0x00024e80 - 0x00024e7f
section, .data: 0x00024e80 - 0x00027197
section, .data1: 0x00027198 - 0x000271bf
section, .ctors: 0x000271c0 - 0x000271bf
section, .dtors: 0x000271c0 - 0x000271bf
section, .eh_frame: 0x000271c0 - 0x000271c3
section, .mmu_tbl0: 0x00028000 - 0x0002800f
section, .mmu_tbl1: 0x00029000 - 0x0002afff
section, .mmu_tbl2: 0x0002b000 - 0x0002efff
section, .preinit_array: 0x0002f000 - 0x0002efff
section, .init_array: 0x0002f000 - 0x0002f007
section, .fini_array: 0x0002f008 - 0x0002f047
section, .sdata: 0x0002f048 - 0x0002f07f
section, .sbss: 0x0002f080 - 0x0002f07f
section, .tdata: 0x0002f080 - 0x0002f07f
section, .tbss: 0x0002f080 - 0x0002f07f
section, .bss: 0x0002f080 - 0x0003477f
section, .heap: 0x00034780 - 0x0003677f
section, .stack: 0x00036780 - 0x0003977f

0% 0MB 0.0MB/s ??:?? ETA
51% 0MB 0.2MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/ipi_app_basic.elf


targets -set -filter {name =~"*A53*0"}

con


disconnect

step finished

Info: This step started at: 2019-06-28 11:59:52
Writing: '33'

Info: This step started at: 2019-06-28 11:59:54
Writing: '99'

Info: This step started at: 2019-06-28 12:00:14
Writing: 'AA'

Info: This step started at: 2019-06-28 12:00:19
Writing: 'CC'

Info: This step started at: 2019-06-28 12:00:21
Writing: 'GG'

step finished

Error: Could not find regular expression in step 0 of test 8 - "(.*)All\s+Tests\s+Complete:\s+IIC\s+PASSED"

Error: Could not find regular expression in step 0 of test 8 - "(.*)###\s+PL\s+DDR4\s+Memory\s+Test\s+finished\s+successfully\s+###"

Error: Could not find regular expression in step 0 of test 8 - "(.*)###\s+PL\s+BRAM\s+Memory\s+Test\s+finished\s+successfully\s+###"

Error: Could not find regular expression in step 0 of test 8 - "(.*)Clocking\s+Test\s+Passed"

Error: Could not find regular expression in step 0 of test 8 - "(.*)System\s+Monitor\s+Example\s+passed!"

Error: Could not find regular expression in step 0 of test 8 - "(.*)The\s+Current\s+Temperature\s+is\s+[3-6]\d.\d\d\d\s+Centigrades"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Fail
Info: Result for step 3: Fail
Info: Result for step 4: Fail
Info: Result for step 5: Fail
Info: Result for step 6: Fail

Info: The test took 0 hours, 01 minutes, and 07 seconds. 0:01:07

Info: PING test started...

Info: The test will take 0 hours, 00 minutes, and 36 seconds. 0:00:36

Info: This step started at: 2019-06-28 12:00:42

Info: This step started at: 2019-06-28 12:00:42

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}

rst -srst


fpga -state
FPGA is not configured

targets -set -filter {name =~"*APU*"}

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init

after 1000

psu_ps_pl_isolation_removal

after 1000

psu_ps_pl_reset_config

catch { psu_protection }
0
targets -set -filter {name =~"*A53*0"}

rst -processor

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/lwip_echo_server.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/lwip_echo_server.elf
section, .text: 0x00000000 - 0x00018fcb
section, .init: 0x00019000 - 0x00019033
section, .fini: 0x00019040 - 0x00019073
section, .note.gnu.build-id: 0x00019074 - 0x00019097
section, .rodata: 0x00019098 - 0x00019daf
section, .rodata1: 0x00019db0 - 0x00019dbf
section, .sdata2: 0x00019dc0 - 0x00019dbf
section, .sbss2: 0x00019dc0 - 0x00019dbf
section, .data: 0x00019dc0 - 0x0001bc07
section, .data1: 0x0001bc08 - 0x0001bc3f
section, .ctors: 0x0001bc40 - 0x0001bc3f
section, .dtors: 0x0001bc40 - 0x0001bc3f
section, .eh_frame: 0x0001bc40 - 0x0001bc43
section, .mmu_tbl0: 0x0001c000 - 0x0001c00f
section, .mmu_tbl1: 0x0001d000 - 0x0001efff
section, .mmu_tbl2: 0x0001f000 - 0x00022fff
section, .preinit_array: 0x00023000 - 0x00022fff
section, .init_array: 0x00023000 - 0x00023007
section, .fini_array: 0x00023008 - 0x00023047
section, .sdata: 0x00023048 - 0x0002307f
section, .sbss: 0x00023080 - 0x0002307f
section, .tdata: 0x00023080 - 0x0002307f
section, .tbss: 0x00023080 - 0x0002307f
section, .bss: 0x00200000 - 0x0061013f
section, .heap: 0x00610140 - 0x0061a13f
section, .stack: 0x0061a140 - 0x0062513f

0% 0MB 0.0MB/s ??:?? ETA
79% 0MB 0.2MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/lwip_echo_server.elf

targets -set -filter {name =~"*A53*0"}

con

after 2000

disconnect

step finished

Info: This step started at: 2019-06-28 12:00:57

Info: This step started at: 2019-06-28 12:01:58

Error: Stopped because step 0 failed in test 6

step finished

Error: Could not find regular expression in step 0 of test 6 - "(.*)IIC\s+PHY\s+reset\s+on\s+ZCU102\s+successful"

Error: Could not find regular expression in step 0 of test 6 - "(.*)\-\-\-\-\-lwIP\s+TCP\s+echo\s+server\s+\-\-\-\-\-\-"

Error: Could not find regular expression in step 0 of test 6 - "(.*)TCP\s+packets\s+sent\s+to\s+port\s+6001\s+will\s+be\s+echoed\s+back"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Start\s+PHY\s+autonegotiation"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Waiting\s+for\s+PHY\s+to\s+complete\s+autonegotiation"

Error: Could not find regular expression in step 0 of test 6 - "(.*)[Aa]utonegotiation\s+complete"

Error: Could not find regular expression in step 0 of test 6 - "(.*)link\s+speed\s+for\s+phy\s+address\s+\d+\:\s+1000"

Error: Could not find regular expression in step 0 of test 6 - "(.*)DHCP\s+Timeout"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Configuring\s+default\s+IP\s+of\s+192\.168\.1\.10"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Board\s+IP:\s+192\.168\.1\.10"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Netmask\s+:\s+255\.255\.255\.0"

Error: Could not find regular expression in step 0 of test 6 - "(.*)Gateway\s+:\s+192\.168\.1\.1"

Error: Could not find regular expression in step 0 of test 6 - "(.*)TCP\s+echo\s+server\s+started\s+@\s+port\s+7"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Fail
Info: The test took 0 hours, 01 minutes, and 17 seconds. 0:01:17

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Xilinx Employee
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Registered: ‎06-21-2018

Re: ZCU102 Board Interface Test Failures

Hi Nicholas,

You want to make sure that you're using the SiLabs driver v6.7.0.0:

https://www.xilinx.com/support/answers/69258.html

Thanks,
Andres

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi Andres,

I just tried with the SiLabs driver v6.7 and the same tests are still failing.

Thanks,

Nicholas

 

Here is the new RTC log:

Info: ZCU102 RTC test started...

Info: The test will take 0 hours, 00 minutes, and 38 seconds. 0:00:38

Info: This step started at: 2019-06-28 17:54:50

Info: This step started at: 2019-06-28 17:54:50

catch { disconnect }
1

connect -url tcp:127.0.0.1:3121
tcfchan#0
targets -set -filter {name =~"*APU*"}


rst -srst

fpga -state
FPGA is not configured

fpga -file {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../bitstream/zcu102_ipi.bit}

initializing
0% 0MB 0.0MB/s ??:?? ETA
4% 1MB 2.2MB/s ??:?? ETA
7% 1MB 1.9MB/s ??:?? ETA
10% 2MB 1.8MB/s ??:?? ETA
14% 3MB 1.8MB/s ??:?? ETA
17% 4MB 1.7MB/s ??:?? ETA
21% 5MB 1.7MB/s 00:11 ETA
25% 6MB 1.7MB/s 00:11 ETA
29% 7MB 1.7MB/s 00:10 ETA
33% 8MB 1.7MB/s 00:09 ETA
37% 9MB 1.7MB/s 00:09 ETA
41% 10MB 1.7MB/s 00:08 ETA
45% 11MB 1.7MB/s 00:08 ETA
49% 12MB 1.7MB/s 00:07 ETA
52% 13MB 1.7MB/s 00:07 ETA
56% 14MB 1.7MB/s 00:06 ETA
60% 15MB 1.7MB/s 00:05 ETA
63% 16MB 1.7MB/s 00:05 ETA
67% 17MB 1.7MB/s 00:04 ETA
71% 18MB 1.7MB/s 00:04 ETA
74% 18MB 1.7MB/s 00:03 ETA
78% 19MB 1.7MB/s 00:03 ETA
82% 20MB 1.7MB/s 00:02 ETA
86% 21MB 1.7MB/s 00:02 ETA
89% 22MB 1.7MB/s 00:01 ETA
93% 23MB 1.7MB/s 00:01 ETA
96% 24MB 1.7MB/s 00:00 ETA
100% 25MB 1.7MB/s 00:14

fpga -ir-status
IR STATUS: 117
Always One (Bits [0]): 1
Always Zero (Bits [1]): 0
ISC_Done (Bits [2]): 1
ISC_Enabled (Bits [3]): 0
Init Complete (Bits [4]): 1
DONE (Bits [5]): 1
(Bits [11:6]): 1
fpga -state
FPGA is configured

targets -set -filter {name =~"*APU*"}

source {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../tcl/ipi_psu_init.tcl}

psu_init


psu_ps_pl_isolation_removal


psu_ps_pl_reset_config

catch { psu_protection }
0
targets -set -filter {name =~"*A53*0"}

rst -processor

dow {C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/../elf/hello_rtc.elf}

Downloading Program -- C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_rtc.elf
section, .text: 0x00000000 - 0x000031d3
section, .init: 0x00003200 - 0x00003233
section, .fini: 0x00003240 - 0x00003273
section, .note.gnu.build-id: 0x00003274 - 0x00003297
section, .rodata: 0x00003298 - 0x000035ef
section, .rodata1: 0x000035f0 - 0x000035ff
section, .sdata2: 0x00003600 - 0x000035ff
section, .sbss2: 0x00003600 - 0x000035ff
section, .data: 0x00003600 - 0x00003ef7
section, .data1: 0x00003ef8 - 0x00003eff
section, .ctors: 0x00003f00 - 0x00003eff
section, .dtors: 0x00003f00 - 0x00003eff
section, .eh_frame: 0x00003f00 - 0x00003f03
section, .mmu_tbl0: 0x00004000 - 0x0000400f
section, .mmu_tbl1: 0x00005000 - 0x00006fff
section, .mmu_tbl2: 0x00007000 - 0x0000afff
section, .preinit_array: 0x0000b000 - 0x0000afff
section, .init_array: 0x0000b000 - 0x0000b007
section, .fini_array: 0x0000b008 - 0x0000b047
section, .sdata: 0x0000b048 - 0x0000b07f
section, .sbss: 0x0000b080 - 0x0000b07f
section, .tdata: 0x0000b080 - 0x0000b07f
section, .tbss: 0x0000b080 - 0x0000b07f
section, .bss: 0x0000b080 - 0x0000b13f
section, .heap: 0x0000b140 - 0x0000d13f
section, .stack: 0x0000d140 - 0x0001013f

0% 0MB 0.0MB/s ??:?? ETA
100% 0MB 0.2MB/s 00:00

Setting PC to Program Start Address 0x00000000
Successfully downloaded C:/Users/nicholasluong/Desktop/Xilinx/ZCU102/zcu102_bit/tests/ZCU102/elf/hello_rtc.elf


targets -set -filter {name =~"*A53*0"}

con


disconnect

step finished

step finished

Error: Could not find regular expression in step 0 of test 2 - "(.*)Last\s+set\s+time\s+for\s+RTC\s+is"

Error: Could not find regular expression in step 0 of test 2 - "(.*)RTC\s+time\s+after\s+set\s+is"

Error: Could not find regular expression in step 0 of test 2 - "(.*)YEAR\:MM\:DD\s+HR\:MM\:SS"

Info: Result for step 0: Fail
Info: Result for step 1: Pass

Info: The test took 0 hours, 00 minutes, and 35 seconds. 0:00:35

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Xilinx Employee
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Registered: ‎06-21-2018

Re: ZCU102 Board Interface Test Failures

Hi Nicholas,

Have you confirmed that you have the right System Controller Firmware? You can do this by connecting through COM Port #3 as explained on XTP433:

System Controller FW 1.pngSystem Controller FW 2.png

 

Thanks,
Andres

 

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1,049 Views
Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi Andres,

Yes, I believe the firmware is up to date.

Here is what it returns:

@ver
Jul 5 2017 11:32:33
>

Thanks,
Nicholas

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Xilinx Employee
Xilinx Employee
1,042 Views
Registered: ‎06-13-2018

Re: ZCU102 Board Interface Test Failures

Hello @nicholasluong,

As you mentioned ZCU102 RTC, MIG PS DDR4, PING, UART 01/02 TEST and IPI Test are failing.

1. Can you please share the complete image of the board when power is ON?

2. Please let us know the status of the power good LEDs?

3. Please check is your ZCU102 Evaluation Kits labeled 0432055-05? If yes Please check below forum thread:

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU102-failed-board-interface-test/td-p/967351

4. Are you using the non-Engish OS? If yes this could be the cause of ping test failure. Please check https://www.xilinx.com/support/answers/69745.html.

5. Please check, which version of the silicon lab has been installed in the machine. It should be 6.7.0.

6. Please share the screenshot the BIT test GUI when tests are failing with there log file.

Regards,

Naveen 

---------------------------------------------------------------------------------------------

Please reply or give kudo or Accept as a Solution.

----------------------------------------------------------------------------------------------

 

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Re: ZCU102 Board Interface Test Failures

Hi @nmanitri ,

Sorry for the delay.

1. The board is exactly how it came out of the box. SW6 is set to JTAG boot mode, as instructed in the ZCU102 Board Interface Test document. Attached is a picture of the board after powered on, before begining any testing.

2. Power Good LED's are all on.

3. Kit is labeled 0432055-05-1849. I am using Vivado 2019.1. Will the FSBL source files in AR-72113 work for me?

4. I am using Windows 10 English OS.

5. Confirmed 6.7.0, see screenshot.

6. BIT test GUI screenshot and log file attached.

Thanks,

Nicholas

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Xilinx Employee
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Re: ZCU102 Board Interface Test Failures

Hi Nicholas,

The paths in your log look different than mine.

Are you using the latest executable from here?:
https://www.xilinx.com/member/forms/download/design-license.html?cid=7c97be6d-60f8-4ce9-a4ac-5c018d49eae4&filename=rdf0377-zcu102-bit-c-2018-3.zip

Please run that one and hopefully we get a "one to one" comparison.

Thanks,
Andres

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi Andres,

I was actually using the 2018-2 version found here: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0048-zcu102-evaluation-kit-hub.html

Just ran the 2018-3 version you provided and UART 01/02 now passes, but the others still fail. Attached is screenshot and log file.

Thanks,

Nicholas

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Xilinx Employee
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Re: ZCU102 Board Interface Test Failures

Hello @nicholasluong 

Due to an End of Life notification from Micron Technology, Inc. the DDR4 SODIMM part on the ZCU102 Evaluation Kit has changed. For more information please check AR-71961.

  • ZCU102 Evaluation Kits labeled 0432055-01 through 0432055-04 are shipped with SODIMM MTA8ATF51264HZ-2G6B1.
  • ZCU102 Evaluation Kits labeled 0432055-05 onward are shipping with SODIMM MTA4ATF51264HZ-2G6E1.

You need to replace the FSBL source code file. Please check AR-72113. To work around this issue, you can replace the FSBL source code files with the attached .c/.h files in 72113-files.zip. 

NOTE: This FSBL source file is only for Vivado 2018.3. Prior to Vivado 2018.3, customer needs to modify the DDR Configuration setting manually and then, they need to generate the FSBL source code File.

Please find the modified DDR configuration settings.

Capture.PNG

I believe this is a known issue. Please check below thread. I will check this issue with our internal experts and let you know.

https://forums.xilinx.com/t5/Evaluation-Boards/ZCU102-Board-User-Interface-test-failed/m-p/981264#M22543

Hope this information will help you. Looking forward to hearing from you.

Regards,

Naveen

---------------------------------------------------------------------------------------------

Please reply or give kudo or Accept as a Solution.

----------------------------------------------------------------------------------------------

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi @nmanitri ,

I am using Vivado 2019.1. Are the FSBL source files good for Vivado 2019.1? I see the thread you sent says "this issue has been resolved in Vivado 2019.1". Additionally, AR72113 says "This issue is planned to be fixed starting in Vivado 2019.1."

Please let me know what actions to take since I am using Vivado 2019.1.

Thanks,

Nicholas

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Xilinx Employee
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Re: ZCU102 Board Interface Test Failures

Hi Nicholas,

As far as I can tell, this issue is not related to the DDR SODIMM. 

I went through your Log and found 4 times this string: "Could not connect to Serial Port. Is it being held up by another program?"

Can you try again making sure that all Terminals are close and you still have the 6.7.0.0 driver? The downloaded file should work in those conditions, without needing to make any additional changes, it does for me.

Thanks,
Andres

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Andres,

Yes, I still have the 6.7.0.0 driver. See screenshot attached.

All terminals should be closed. I just restarted my computer and ran the Board Interface Tests again with the same failures. Log file is attached.

Also I am able to talk to the board using the System Controller, making me think the ports are not held up by another program. Let me know your thoughts.

Thanks,

Nicholas

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Re: ZCU102 Board Interface Test Failures

Hi Nicholas,

What do you mean by "I am able to talk to the board using the System Controller"?

That you can inquire the FW version by doing "@ver"?

Thanks,
Andres

 

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi Andres,

Sorry, to be more clear, the board responds when using the System Controller tab of the Board User Interface (BoardUI.exe version 2018-3). For examle I can set & read the clocks, GTR MUX, read the voltages, power, EEPROM data, temperatures, and GPIO's. One thing I noticed, though, is the Si570 User Frequency gets set to 0MHz (from 300MHz) after reading PS or PL Side Power.

Yes, I can inquire the FW version by doing "@ver". See screenshot attached.

Thanks,

Nicholas

@ver.PNG
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Xilinx Employee
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Re: ZCU102 Board Interface Test Failures

Hello @nicholasluong,

I am checking this information with our Development Team. For that, I need the following details from you:

1.  Please share the specific SODIMM part number being used in the failing board.

2. Can you please check which DDR memory is there inside the SODIMM? Is it Micron or Kingston? Please open the cage and check this. 

3. Have you tried to run the lastest BIT test? If yes, is it failing? Please confirm.

Regards,

Naveen

 

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi @nmanitri ,

1. SODIMM PN: MTA4ATF51264HZ-2G6E1

2. Micron. Screenshot attached.

3. The latest BIT test I've run is version 2018-3. Failures are logged on my earliler post from ‎07-02-2019 09:59 AM. I just ran again with same results. Screen cap and log file attached.

Thanks,

Nicholas

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Registered: ‎06-28-2019

Re: ZCU102 Board Interface Test Failures

Hi @nmanitri ,

Any updates from the dev team?

Thanks,

Nicholas

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