02-18-2019 05:10 PM
I have a brand new ZCU102 EVM and I'm following displayport subsystem 1.4 user guide example design. I was using TX only design. The bit file was generated suscessfully. In SDK, I was able to import example of xdptxss_zcu102_dp14_tx, build was successful.
When I run it, nothing shows up on Tera term.
Then I run in debug mode, CortexR0 #0 is running and not stopping at main(). I paused it, it stops at function Xil_DCacheInvalidateRange.
Could you help to see what issue it is?
I'm using vivado 2018.2 in windows10.
02-18-2019 10:59 PM
I'm not familier with ZCU102.
But I'd like to know the followings to find the route cause.
- What monitor do you use ?
- How do you connect to monitor ? DP cable or other ?
- What resolution do you want to output ?
- How do you set resolution and video timing ?
02-19-2019 02:29 AM
02-19-2019 11:09 AM
I have FMC card and I can change VADJ to 1.8V. However, the problem is not related to the video setup. The program didn't get to main(), no application code was run.
I found someone complain similar issue, as shown in the link:
It seems board related. My board has all power LEDs on. The "DONE" light is up after prgram with FPGA bit file.
Maybe the linker file change can help, but I don't know how.
Thanks and Regards,
02-19-2019 03:24 PM - edited 02-19-2019 03:27 PM
02-19-2019 04:21 PM
I wasn't using linux. I was using windows 10, vivado 2018.2 and SDK. I suspect the issue is that ddr is not properly trained and the starting address in ddr is not accepted.
Thanks and Regards,
02-22-2019 09:18 AM
Just to follow up this thread, I finally get the displayport example design working, by modifying the linker file. As discussed in this thread:
It turned out that ZCU102 new boards have ddr4 software in-compatible issue. I have to run code from ocm instead of ddr4.
It's disappoiting the xilinx is not responding to the issue.
02-22-2019 09:58 AM
02-22-2019 04:03 PM
Thanks for the information, it clearly described the issue but the solution is not clear to me.
I installed 2018.3 vivado and sdk. According to the thread, I need to generate FSBL.
I created FSBL project following the link below:
I rebuilt my project (I didn't understand here how my project get affected by the new built fsbl project), anyway, as I run in debug mode, it did stop at main() but only showing Dissembly. As I stepped a few more steps, I got error " AP transaction error, DAP status 30000021"
Is there more clear instructions on how to do it?
One specific question is when generating the project, in the Target Hardare selection:
for my application, I pick the **_wapper_hw_platform_0, for generating FSBL, I selected ZCU102_hw_platform, is this correct?
02-26-2019 10:02 AM
To follow up, the issue was resolved by following suggestions in this link: