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mosaix
Observer
Observer
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Registered: ‎11-17-2009

ZCU102 Ethernet PHY strap configuration resistors

I am designing a custom board that is based on Xilinx's ZCU102 development board and have a question regarding the DP838671IR Ethernet PHY strapping pins. See page 41 of the ZCU102 schematics on page 41.

 

What is confusing is that the values used for the pull-up and pull-down strapping resistors on the DP838671IR strapping pins in no way resemble Texas Instruments' suggested values. See page 45 of the DP838671IR datasheet.

 

For a PHY address of 0x0C, RX_D0 should be in Mode 0 and RX_D2 should be in Mode 4 which according to the TI datasheet means that the following:

1.  pullup on RX_D0 should be OPEN and the pull-down should be OPEN

2. pullup on RX_D2 should be 2.49KOhm and the pull-down should be OPEN.

 

However, the ZCU102 schematics show the following connections

1.  pullup on RX_D0 is  OPEN and the pull-down is 1K Ohm

2. pullup on RX_D2 is KOhm and the pull-down is OPEN.

 

Not clear why the schematics deviated from the TI specs. Are the schematics incorrect? Am i missing something?

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kvasantr
Moderator
Moderator
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Registered: ‎04-12-2017

Hello @mosaix,

 

I will recommend to follow the design guidelines as mentioned in the  user guide of the peripherals used along with the Xilinx devices.

We will not recommend to refer the evaluation board schematics for product development.

 

Please check PCB design guidelines of Xilinx UG583, XTP427 and design guidelines of peripheral mentioned in there respective user guide.

 

Thank you.

 

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mosaix
Observer
Observer
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Registered: ‎11-17-2009

Thanks for taking the time to reply.

Unfortunately I find your answer vague and unhelpful at best. A good engineer will want to understand why your ZCU102  board designer made those decisions that seem to contradict the recommendations of the TI  datasheet. Maybe there is a very good reason.  Alternatively, maybe this is a mistake that slipped through the cracks during design review. I have checked a number of different Xilinx board schematics (i.e. like the ZCU104 for example)  and the same issue is repeated there too.

So the question remains - why did your board designer deviate from the TI recommended pin strapping settings?

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