11-27-2017 11:50 PM
I'm having some issues with the transceivers connected to the FMC connector on the ZCU102 evaluation board.
I have a loop-back FMC card that works just fine on other evaluation and custom boards but on this evaluation board, when I use an IBERT test, the EYE is very (very) poor. This is the best EYE that I managed to get:
Are there any known issues with this board regarding the transceivers in general and the ones that are connected to the FMC connector in particular?
11-28-2017 07:49 AM
Are you saying this works on other ZCU102 boards but not this one?
That would most likely be a bad (or damaged) board situation. Was the board handled properly regarding ESD protections? (Always using a ESD safe workbench, grounding straps, etc.?)
11-28-2017 07:55 AM
What is the line rate you are using? You should probably also do a sweep of a few TX amplitudes and try both LPM and DFE equalization.
12-03-2017 05:20 AM
I'm comparing this evaluation board to other evaluation boards (other FPGA like kintex7 ultra scale and Virtex7 ultrascale +).
I have 2 ZYNQ ultrascale+ evaluation boards and they act the same.
The maximum line rate is ~6Gbps, through the FMC connector.
12-04-2017 11:49 AM
Did you use the same FMC connector on both boards, or did you try different FMC connectors? It would be good to narrow down the problem to FMC connector, or the ZCU102 boards. It sounds like the same issue appeared on two ZCU102 boards, but i wanted to confirm that the test was using the same FMC with both board tests.
12-07-2017 03:01 AM
Yes, I tested this with the same FMC mezzanine card.
I have 2 ZYNQ evaluation boards, rev 1.0 and rev 1.1.
I'm seeing the same issue on both boards and on both FMC connectors on those boards.
12-13-2017 03:45 PM - edited 12-13-2017 03:50 PM
This is not a known issue with the board but I'm not sure how well tested the FMC connections are. My thinking is that it is an issue with the setup of the channel. Did changing DFE to LPM or changing amplitude have an effect? Is near end PMA loopback working?
12-13-2017 11:59 PM
12-14-2017 08:47 AM
Are you sure you have a good reference clock? Is it coming from this FMC card? Is it the same generator used in your other tests?
It would be good to know if turning down the equalization further helps. Override the RXLPM_HF_CFG and RXLPM_LF_CFG values and set them to 0. (Page 191 of UG576)
12-16-2017 10:33 PM
Yes, the clock is good, the source is a 125MHz oscillator that is located on the FMC card.
Yes, this is the same card that I'm using with all other boards.
is it possible to overwrite those parameters for the IBERT design? If so, how?