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Contributor
Contributor
175 Views
Registered: ‎10-17-2013

ZCU102 board ,aurora-8b10b implementation failed on 50% ;

question:  I use aurora8b10b IP on zcu102 board;  It failed on 50%(impl) when do implementation  ; 

log is as below: 

[Place 30-682] Sub-optimal placement for a GT-BUFG_GT component pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0]] >

Then , I used below constraint as message refered , it stoped at 80% , 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[1]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[2]]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[3]]

The Full constraint .xdc file content is as below:

create_clock -period 13.468 -name auro_init_clk -waveform {0.000 6.734} [get_ports usr_ref_p_i]
create_clock -period 6.400 -name GT_REFCLK1 [get_ports gt_refclk1_p_i]

set_property PACKAGE_PIN AK15 [get_ports usr_ref_p_i]
set_property PACKAGE_PIN AK14 [get_ports usr_ref_n_i]
set_property PACKAGE_PIN N27 [get_ports gt_refclk1_p_i]
set_property PACKAGE_PIN N28 [get_ports gt_refclk1_n_i]

set_property IOSTANDARD LVDS_25 [get_ports usr_ref_p_i]
set_property IOSTANDARD LVDS_25 [get_ports usr_ref_n_i]

 

The full message failed at impl 50% is :

[Place 30-682] Sub-optimal placement for a GT-BUFG_GT component pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0]] >

u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y4
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y32

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufds_gthchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent two clock
regions (top/bottom)
u0_pl/u0_aurora/aurora_module_i/IBUFDS_GTE4_refclk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X0Y1
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y5
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y6
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y4
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X0Y7

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y4
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) cannot be placed

Clock Rule: rule_gt_bufggt
Status: FAIL
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y5
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y30
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[1]] >

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y5
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CLK) cannot be placed

Clock Rule: rule_gt_bufggt
Status: FAIL
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y6
u0_pl/u0_aurora/aurora_module_i/clock_module_i/user_clk_buf_i (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y37
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y26
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[2]] >

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y6
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_2 (BUFG_GT_SYNC.CLK) cannot be placed

Clock Rule: rule_gt_bufggt
Status: FAIL
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y7
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y29
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[3]] >

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X0Y7
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_3 (BUFG_GT_SYNC.CLK) cannot be placed

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) cannot be placed
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y32

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CESYNC) cannot be placed
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y30

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_2 (BUFG_GT_SYNC.CESYNC) cannot be placed
u0_pl/u0_aurora/aurora_module_i/clock_module_i/user_clk_buf_i (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y37
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y26

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_3 (BUFG_GT_SYNC.CESYNC) cannot be placed
and u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_cpll_cal_gthe4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_inst/gtwizard_ultrascale_v1_7_3_gthe4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y29

 

 

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Registered: ‎10-17-2013

Re: ZCU102 board ,aurora-8b10b implementation failed on 50% ;

The Full message when failed at 80%(impl)  is : 

[Route 35-54] Net: u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[0] is not completely routed.

[Route 35-54] Net: u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[2] is not completely routed.

[Route 35-54] Net: u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[1] is not completely routed.

[Route 35-54] Net: u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[3] is not completely routed.

 

[DRC RTSTAT-1] Unrouted nets: 4 net(s) are unrouted. The problem bus(es) and/or net(s) are u0_pl/u0_aurora/aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_gt_i/inst/gen_gtwizard_gthe4_top.aurora_8b10b_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/txoutclk_out[3:0].

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