Hello There,
I may have found a problem in pin assignment in the documentation provided by Xilinx for ZCU104 evaluation kit (https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0093-zcu104-evaluation-kit-hub.html)
For instance:
- The ug1267-zcu104-eval-bd.pdf specifies DDR4_SODIMM_DQ0 assigned to AG14 pin.
- The ZCU 104 schematic specified DDR4_SODIMM_DQ0 assigned to AE24 pin.
The others pins assignment does neither look consistent.
Can any Xilinx employee confirm if I missunderstood something or if there is a problem in the documentation?
