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Registered: ‎07-16-2015

ZCU111 ADC Clock PLL Lock

Hi everyone,

I recently started working with the ZCU111 board and I am having some problems trying to make my own design work. I think it is related with the external configuration of the LMX PLLs, but I am not sure.

The board itself works without problems with the "RF Data Converter Evaluation Tool" and I can stream data and read it back with the GUI.

I tried to keep my design as simple as possible to minimize the points of failure. My design looks like this:

  • One ADC active with internall PLL (configured to expect a 245.76 Mhz input clock and sampling rate of 3.19488Gsps) - Just like the TRD.
  • One MMCM at the output clock (clk_adc0) to increase the frenquency and match the requirements of the AXI4-Stream of the ADC (Figure 72 on PG269)
  • One ILA core clocked from the output of the MMCM

To configure the external PLLs (LMK and LMX) I used the SCGUI with the following files:

  • ZCU111_RevA_01132018_U90_122.88MHz.txt
  • LMX2594_245M76.txt - Generated from LM2594_0245M76.tcs with the TICS Pro software as explained in this post.

I tried reprogramming the FPGA afer the PLLs configuration but there is no way to get a clock at the clk_adc0 output.

On the board I can see the 4208_STATUS, MUXOUT_RF1, MUXOUT_RF2, MUXOUT_RF3 lighting up after my configuration, so I assume the PLLs are locked and the ADC receives a stable clock. 

Does the ADC block needs some kind of Software intervention to bring it out of the reset state? Is there some guide how to trobuleshoot the ADC Clocking problems?

I tried bypassing the internal PLL but also no output clock.

I also tried adding a JTAG-to-AXI IP clocked from the external fixed 100Mhz clock to read the status register of  but the ADC IP doesn't answer (I always receive a timeout)

Any ideas how to proceed with the debugging?


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Registered: ‎10-19-2011

What exactly isnt working with your custom design? What do you get from getblockstatus?

Don’t forget to reply, kudo, and accept as solution.
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