I'm having troubles with clock instability on the zcu111 board. With the programmable logic I measure the phase of an input signal. If the board clock is synched to an external reference, I see in the measured phase an increased noise and some big spikes that repeat regularly at about 1 Hz rate. Right before each spike I can see an oscillation that gradually builds up over a time of about 100 ms. If I switch to internal reference clock the spikes are gone, however I still see some small oscillations in the measured phase. I've tried many different external reference sources, and I've configured the LMK so that all the PLL settings are exactly the same for internal or external reference.
I suspect that the capacitors and resistors for the loop filters of the LMK on the zcu111 are not optimally dimensioned. This causes the phase margin of the PLL2 to be too low and therefore the device is operating close to instability. This gives the small phase oscillations I see when using internal reference, and the big spikes when using external reference (due to extra loading from the cable, extra noise and/or disturbances). Does this make sense?
To give some detail, I've programmed the LMK04208 to accept a 12.8 MHz input either from the built-in TCXO (CLKin0) or from J109 (CLKin1), and to output 10 MHz to J108 (CLKout5), 64 MHz to the programmable logic (CLKout2) and 122.88 MHz to the lmx chips (CLKout4). I'm using the VCXO at 122.88 MHz built in to the zcu111, and the lmk-internal VCO is running at 2880 MHz. The phase-detector frequency for the PLL1 is 2.56 MHz and for PLL2 is 3.84 MHz. The choice of CLK input is done manually by loading a different configurtion into the LMK, to rule out the possibility of automatic switching.
Using the Clock Architect tool by Texas Instruments, I obtain that the optimal values for the PLL2 loop bandwidth are C1 = 10 pF, C2 = 1.5 nF and R2 = 4.7 kohm, which would give a loop bandwidth of 76 kHz and a phase margin of 70 deg. However, from the schematics for the zcu111 board (0381811_ZCU111_REV1_0_07122018.pdf) I can see that these components have rather different values: C1 = 18 pF (C773), C2 = 2.2 nF (C772) and R2 = 1 kohm (R650), which result in a loop bandwidth of 35 kHz and phase margin 26 deg (really low!).
The components for the PLL1 loop filter are also very different from the ones suggested from the TI tool: optimal values are C1 = 22 nF, C2 = 1 uF and R2 = 6.8 kohm, however on the zcu111 there are C1 = 0.68 nF (C778), C2 = 0.033 uF (C777) and R2 = 220 kohm (R651). The deteriortion of loop bandwodth and phase margin can in this case be mitigated by decreasing te charge pump gain, so that's not as critical as the PLL2 loop filter.
Is there a reason for dimensioning the loop filters so far from the values suggested by the Clock Architect? Or is it just a design mistake?