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Contributor
Contributor
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Registered: ‎09-18-2018

ZCU111 RFDC - Understanding SYSREF input in this reference design

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Hi All,

I am in the process of becoming familiar with the RFDC module on the ZCU111 evaluation board. I am currently trying to work through the examples written by @klumsde in RF Data Converter Software Drivers - Really Foolproof, not Really Frustrating. I'm at the section 'Hello RFDC' and I can see that that the reference design has 3 inputs: adc0_clk_0, vin0_01_0 and sysref_in_0.

Where do those inputs come from? Where should I connect them to?

image.png

I'm looking at the constraints file attached at the end of the blog post and it makes no mention of these ports, and after scouring UG1309 and PG269 I still have no idea how to hook them up.

Using Vivado 2018.3

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Moderator
Moderator
373 Views
Registered: ‎04-18-2011

Re: ZCU111 RFDC - Understanding SYSREF input in this reference design

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adc0_clk_0 is the clock input to the ADC tile 0. This will come from the LMK RF PLL on the board. 

vin0_01_0 is the analog input to the ADC0 in ADC tile 0. This will come in via Balun path on the XM500. In this case you can provide this from your signal generator.

sysref_in_0 is the Sysref input to the the Data converters as a timing reference for multi-tile synch. 

These are all fixed on the board so there is no need to constrain them. 

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Moderator
Moderator
374 Views
Registered: ‎04-18-2011

Re: ZCU111 RFDC - Understanding SYSREF input in this reference design

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adc0_clk_0 is the clock input to the ADC tile 0. This will come from the LMK RF PLL on the board. 

vin0_01_0 is the analog input to the ADC0 in ADC tile 0. This will come in via Balun path on the XM500. In this case you can provide this from your signal generator.

sysref_in_0 is the Sysref input to the the Data converters as a timing reference for multi-tile synch. 

These are all fixed on the board so there is no need to constrain them. 

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Visitor sungh
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Registered: ‎07-05-2019

Re: ZCU111 RFDC - Understanding SYSREF input in this reference design

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I have another question.

adc0_clk_0 is the clock input to the ADC tile 0. This will come from the LMK RF PLL on the board.

In my understanding, LMK is a clock chip, it will give several  clocking signals.  Does the LMK need external reference clock signal input? 

Or do we just need to configure the chip? Because I saw the SMA input interface for the reference clock on the card. 

UG1217, page 14: 

J108- RF clocking, U90 LMK04208 RF REFCLK SMA

J109-RF clocking, U90 LMK04208 RF external REFCLK SMA

 

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Moderator
Moderator
234 Views
Registered: ‎04-18-2011

Re: ZCU111 RFDC - Understanding SYSREF input in this reference design

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A new question really belongs in a new post. 

If you look at the clocking structure of the RF PLLs on the board the LMK is a jitter cleaner that takes either TCXO clock or the external reference clock from the SMA header J109forum_zcu111_rfplls.JPG
lmk_input_sch.JPG

 

 

 

To use the external input you need to connect a reference clock to the LMK via J109, pull out J110 to turn off the TCXO. 

You will also have to program the LMK so that it is set up for an external signal 

J108 is the cleaned output of the LMK

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Visitor sungh
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Registered: ‎07-05-2019

Re: ZCU111 RFDC - Understanding SYSREF input in this reference design

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Your answer settled my question very well. I got it. Thanks a lot.

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