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Visitor tommhk2002
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3,613 Views
Registered: ‎01-15-2018

ZYNQ interrupt from PL

How can i interrupt the PS from PL without AXI-GPIO?
For example : My RTL design will send some signal to PS. How can i use these signal to interrupt PS ?
What should i do in SDK?
Thanks a lot!!

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Scholar hbucher
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Registered: ‎03-22-2016

Re: ZYNQ interrupt from PL

@tommhk2002  Here is an example:

https://www.xilinx.com/support/answers/50572.html

 

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Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL

Thanks for reply
In that example , i see some functions related to timer  ex:XTmrCtr_SetHandler , XTmrCtr_Start  in  that c file . these function are  xilinx build-in function for timer.

Does it mean that i have to rewrite these function for my RTL module?

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Scholar hbucher
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Registered: ‎03-22-2016

Re: ZYNQ interrupt from PL

@tommhk2002 No, absolutely not. Those are part of the Xilinx API for the AXI timer.

In this design they use an AXI timer to interrupt the CPU - so they have to set up the timer parameters in software.

In your case, it will your IP so that will not be necessary (it won't even compile because there will be no timer in your design - in principle).

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Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL



is it necessary to use XScuGic_Connect this API ? if not using this API , i dont know how to connect zynq and my ip together.

Also, my IP design ID is generated by tool?

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Scholar hbucher
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Registered: ‎03-22-2016

Re: ZYNQ interrupt from PL

@tommhk2002  Finding the right documentation can be daunting in the beginning - have a look at XAPP 745

https://www.xilinx.com/support/documentation/application_notes/xapp745-processor-control-vhls.pdf

"Interrupt Handling" from page 5 onward explains this in great detail.

 

 

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Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL

Thanks a lot!

Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL

Hi hbucher,
i read your pdf , and i am confused with function ( XScuGic_Connect).
On page 7 and 8,

 

XExample ex;
result = XScuGic_Connect( &ScuGic, XPAR_EXAMPLE_INTERRUPT_INTR, (Xil_InterruptHandler)ExampleISR,&ex);

Type XExample is   generated by Vivado HLS Tool
in my case , ex should be a pointer to my RTL design , but i do not use Vivado HLS Tool , just writing verilog design.
How can i make the Type XExample  without Vivado HLS Tool?

Thanks!

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Scholar hbucher
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Registered: ‎03-22-2016

Re: ZYNQ interrupt from PL

@tommhk2002 You do not need that. The last parameter is an opaque pointer (or integer) supplied by the user to be passed in the callback. 

 

s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, Xil_InterruptHandler Handler, void *CallBackRef);

Check that the "CallBackRef" argument is void-pointer. The example uses that opening to pass a pointer to the object so it can do some housekeeping. But not necessarily. You can pass NULL if you want - the function will not use it.

 

The best documentation is really the header files. The Xilinx developers put a lot of effort to document the APIs in a way that is more accessible than the PDFs - in my opinion.

 

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/scugic/src/xscugic.h

 

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Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL

So far, my rtl design can interrupt PS. but , it seem just level interrupt works.
How can i change to edge interrupt?
the default setting is level interrupt?
Thanks a lot!

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Scholar ericv
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Registered: ‎04-13-2015

Re: ZYNQ interrupt from PL

Hi @tommhk2002

 

The edge / level is set with XScuGic_SetPriorityTriggerType()

It's the 4th argument (Trigger); for edge, supply a value of 3.

 

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Visitor tommhk2002
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Registered: ‎01-15-2018

Re: ZYNQ interrupt from PL

thanks!

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