I'm developing bare metal applications for the Zynq on the ZC702. I'm booting in QSPI mode and I've replaced the FSBL code with a modified version. The problem is that after the BootROM reads the FSBL image and begins execution it seems like only Core0 is beginning execution at address 0x0. Core1 is ending up at address 0xFFFFFF08 running a small block of code. To debug I even modified the FSBL image so that the first thing at address 0x0 is an endless loop. After I boot up the board I connect with a DStream POD using ARM's DS-5 debugger and Core0 is sitting in the endless loop and Core1 is always at address 0xFFFFFF08.
Why isn't Core1 also starting from address 0x0 after the BootROM loads the image from qspi flash? Is there something else I need to do. Every example application including the BOOT.S file from Xilinx has code to detect which core is executing and if it's not core0 it will do an endless loop. That code doesn't work if both cores don't start from the same address after the BootROM does it's soft reset.