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Registered: ‎11-04-2009

ads5282 connected to a Spartan6 LX150T Development board FMC#2 slot


I want to connect ads5282 ADC in a Spartan6 LX150T Development board. While i achieve to connect it to the FMC1 slot correctly i have some questions about connect another ads5282 ADC to the FMC2 slot.

I have use the technique described here http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/47555.aspx to deserialize adc data correctly inside the FPGA for the FMC1 slot and i am trying to do the same for the FMC2 slot.

I read in Spartan6 LX150T Development board manual that the ddr clock is not routed to global CLK pins something that is also confirmed from Spartan 6 LX150T FGG676 package and pinout manual. If this clock is not routed to a global CLK pin then i cannot use it to clock the ddr cells. Is that right?

How can i deserialize  adc data correctly inside the FPGA in this situation?

Also 4 of the 8 adc channels are located to a different bank from the one that the ddr clock  is located. How can i get data from this channels inside the FPGA?



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