03-31-2020 12:39 AM
I am trying to safely change fmc_adj voltage in kc705 from default 2.5V to 1.8V. I am planning to use TI based Fusion Digital Power Designer and usb interface adapter evm to do so. I am not finding proper documentation on how to change parameters through the software, is there any tutorial ? I only see a tutorial on how to restore factory settings through a script which is of not much help.
03-31-2020 12:54 AM
Hi @omar.sheriff ,
To set VADJ Voltage other than default voltage, you need to develop a code. Unfortunately, Xilinx will not give any reference codes. For more information refer page 75 of UG810 (v1.9).
03-31-2020 05:25 AM
-adding to comments of Deepak.
The FMC_VADJ rail powers VCCO for some banks of the FPGA (see Table 1-3 in UG810). So, IOSTANDARD for the IO pins in these banks *must* be compatible with your new voltage for FMC_VADJ. That is, you *must* choose the correct IOSTANDARD for the pins and create the bitstream with the new FMC_VADJ voltage in mind.
Also, when the FPGA is powered ON and using the new bitstream, you *must* prevent FMC_VADJ from powering VCCO of the FPGA banks. When you are sure that the FMC_VADJ voltage is set properly, then you can allow it to power VCCO of the FPGA banks
All-in-all, this seems a dangerous thing to do. I agree with you that Xilinx should provide detailed guidance for doing it – or at least warn us of the dangers.
03-31-2020 12:13 PM
@omar.sheriff Deepak and Mark have pretty much listed the process and necessary precaution to take care of.
Coming to the TI Fusion Digital Power Designer, what is the issue you have in reprogramming the FMC_VADJ rail? Using the "Click to configure device" option, you can change the Vout of the FMC_VADJ regulator along with the necessary parameters. Yes, it is not straight forward and needs you to understand the parameters before changing it. So do go over the flow, make sure you understand what you are changing and using the GUI, you should be able to set the FMC_VADJ rail.
The precautions Mark has stated above do apply to these steps too. Change it "only" after making sure you have the right settings in FPGA.