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Visitor omar.sheriff
Visitor
259 Views
Registered: ‎11-21-2019

how to set programmable user clock on ZC706 board

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Hi,

I am new to FPGA design development, but can someone guide me on how to use the programmable user clocks on Zynq ZC706 ?. I want to generate a 25Mhz clock on my clk pin from the available range of 10Mhz - 810Mhz. 

Regards,

Omar

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Xilinx Employee
Xilinx Employee
112 Views
Registered: ‎02-14-2014

Re: how to set programmable user clock on ZC706 board

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Hi @omar.sheriff ,

Right way to approach this would be -

1. Open project si570_freq.xpr preset in downloaded repository with Vivado 2014.3 and observe what all IP blocks are present in it.

2. Migrate this project to ZC706 and modify system.xdc file accordingly for physical constraints.

3. Generate bitstream and ltx file for this new project and use it in freq_adjust.tcl file.

Regards,
Ashish
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Xilinx Employee
Xilinx Employee
228 Views
Registered: ‎02-14-2014

Re: how to set programmable user clock on ZC706 board

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Hi @omar.sheriff ,

Download this tutorial as a starting point (which can be similarly applied for zc706 board). Tutorial is for KC705 board -

https://www.xilinx.com/member/forms/download/design-license.html?filename=xtp204-kc705-si570-prog-c-2014-3.pdf&cid=370280

Regards,
Ashish
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Visitor omar.sheriff
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161 Views
Registered: ‎11-21-2019

Re: how to set programmable user clock on ZC706 board

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Hi Ashish,

I understand that similar procedure can be followed for ZC706, unfortunately I do not have the same board so the bit stream is incompatible. I can create a .ltx debug file and add it along with my bitstream, but I do not know how to bring up or select the Si570 user clock and system clock debug points. Could you give a description on how I can select these points to be brought up on my debug probe list ?

Thanks & Regards

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Xilinx Employee
Xilinx Employee
113 Views
Registered: ‎02-14-2014

Re: how to set programmable user clock on ZC706 board

Jump to solution

Hi @omar.sheriff ,

Right way to approach this would be -

1. Open project si570_freq.xpr preset in downloaded repository with Vivado 2014.3 and observe what all IP blocks are present in it.

2. Migrate this project to ZC706 and modify system.xdc file accordingly for physical constraints.

3. Generate bitstream and ltx file for this new project and use it in freq_adjust.tcl file.

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post