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Explorer
Explorer
570 Views
Registered: ‎03-18-2008

how to supply 200MHz clock for xilinx DPHY IP application with VCU118 board clock source?

DPHY needs a pair of 200MHz differential clock.

 

how to supply at vcu118 board?

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3 Replies
Moderator
Moderator
513 Views
Registered: ‎08-08-2017

Re: how to supply 200MHz clock for xilinx DPHY IP application with VCU118 board clock source?

Hi @m006

 

VCU118 have system clock of 300 MHz and 125MHz Clock

 

system_clock.PNG

 

Use the below sequence to derive the 200MHz clock from the system clock as follows.

 

 Differential System clock(300Mhz)   -> IBUFDS  -> BUFG -> MMCM to generate 200MHz clock.

 

Instantiation and description of all these primitives are given in Libraries use guide

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug974-vivado-ultrascale-libraries.pdf

 

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Reply if you have any queries, Give Kudos and Accept as solution if you get one

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Reply if you have any queries, give kudos and accept as solution
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Explorer
Explorer
504 Views
Registered: ‎03-18-2008

Re: how to supply 200MHz clock for xilinx DPHY IP application with VCU118 board clock source?

can the two MMCMs be cascaded?

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Moderator
Moderator
456 Views
Registered: ‎08-08-2017

Re: how to supply 200MHz clock for xilinx DPHY IP application with VCU118 board clock source?

Hi @m006

 

Yes . The MMCM can be cascaded through the routing resources only and there is no compensation for routing delays .

 

Refer CMT to CMT connection in Ultrascale and 7 series clocking user guide

https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

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I believe your first query is answered ,Can you please mark it as accepted as solution ..Please let me know if you differ

and need further assistance .

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Reply if you have any queries, give kudos and accept as solution
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