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Newbie ashwini484
Newbie
2,973 Views
Registered: ‎08-03-2017

how to use PS Clock for PL logic

Hello !!

There is no PL fabric clock generated by the PS available in my design.

In my project, I have generated a PS CLK of frequency 50 MHz and assigned it to my IP. I was successful in generating the bit file. But I dont see any output. I did a little bit of debugging and identified that there is no CLK at my input port. Is there any specific way to connect the PS side Clock to the PL side?

Can some please help me out.

Thanks

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1 Reply
Moderator
Moderator
2,967 Views
Registered: ‎11-09-2015

Re: how to use PS Clock for PL logic

Hello @ashwini484,

 

This is a common issue. There are lot of post about this on the forums. For example I have found this one with a quick search on google:

https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Zynq-PL-Fabric-Clocks-FCLK-CLK0-1-2-3-not-coming-through/td-p/464654

 

The PS needs to be configure to have the clock available in the PS.

 

Just create an hello world application in SDK, start to debug it (you don't have to run it, it can stay stopped at the entry breakpoint), then program the FPGA and the clock will be available.

 

The other way is to source the ps7_init.tcl script in xsct but the 1st method is easier for beginners.

1.fpga -f system.bit
2. connect arm hw 
3. source ps7_init.tcl
4. ps7_init

5. ps7_post_config

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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