05-28-2014 08:27 PM
Thanks for the help so far.I am working ZYNQ family ZC706 board
I am actually trying to generate IP core for QUAD_111. I got struck at point,choosing the clock
How much should I select the refernce clock frequnecy if i want to run GTX transceivers at 5 gbps or 6.6 0r 10 . the Gtx SMA clock is connected to QUAD 111. and what should i Specify REFclock source . should i go for MGTREFCLK1_112?
As per the few discussions i feel it.
Can you please answer the same things for quad_109 and quad_110
suppose if i want to run gtx transceivers at 5 or 6 or 10 gbps ? what is the reference frequency should i specify?
what is Rference clock source ?MGTREFCLK1_?
can i also know how to decide the data port width? we usually select the 40 ..
thank you so much
please help me in this regard
05-28-2014 09:26 PM
Have you thought of or have used the "GT WIzard". Because this is something which you clear all the queries which you have.
Open the Coregen tool(ISE) or IP Catalog(Vivado) and check for "7 series FPGA transceiver wizard". This should help you decide the Reference Clock, Width, clock sharing and line rate.
05-28-2014 11:12 PM