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tchin123
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Registered: ‎05-14-2017

mgtclk clock signal format for gte4 in Ethernet IP

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I'm using the axi_ethernet subsystem IP in an Ultracscale+ FPGA and the mgt_clk has PACKAGE_PIN defined but not the IOSTANDARD defined on the Xilinx evaluation board ZCU106 xdc file .

I'm using the Si5328 ethernet clock multiplier to generate the 125 Mhz. This device can generate LVPECK, LVDS, CML, CMOS signal format. Why doesn't the xdc define the IOSTANDARD  for the MGT clock because then I wouldn't know what signal format to select from the Si5328 clock device?

 

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

That's my point - I guess I didn't make it clear.
When you apply an IOSTANDARD to a SelectIO - it is actually changing the configuration of the input buffer, output buffer, etc. in the FPGA configuration.
There is no such flexibility with the GTs - that's why the GT user guides have different recommendations externally (board-level) depending on if the reference clock is LVDS or LVPECL.

There is no FPGA-level programmability on the IOSTANDARD here - that's why it isn't needed or provided.

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roym
Moderator
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Registered: ‎07-30-2007

MGT clocks have to be either LVDS or LVPECL and the same set up can handle either input so there is no IOSTANDARD setting for this pin.  There are no options.  The transceiver user guide will go over the IO standards that are supported.

 




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tchin123
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Registered: ‎05-14-2017

Since there are no IOSTANDARD requirement  for the MGT_CLK, then either LVDS or LVPECL format should work?

But the ZCU106 development board Si5328 device only has a 0.01 uf AC coupled capacitor on the clock out before going to the FPGA mgt_clk pin. From the Ultrascale Architecture GTH transceiver UG576 user guide, under Reference Clock Interface section, isn't this a LVDS connection interface? The LVPECL shows an additional 240-ohm termination. Therefore in this ZCU106 design, shouldn't I specify a LVDS format on the Si5328 device? Or is it possible it doesn't matter, I'm a little confuse. 

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roym
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Registered: ‎07-30-2007

I always recommend LVDS.  I don't believe all LVPECL outputs need the 240 ohms but yes choose LVDS.




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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

A very common point of confusion is the IOSTANDARD (or lack thereof) for the GTs... Unlike the generic and programmable SelectIO (covered in UG571 and UG471 for example for US/US+ and 7 series respectively), the TX and RX diff pairs and REFCLK inputs on this largely analog block (at least to the outside world)  are fixed in function/configuration (typically CML - current mode logic). So there's no need as said above to apply an IOSTANDARD.

For the US/US+ GTH here, see the transceiver user guide on the REFCLK inputs, e.g. pages 327-328 for v1.6:
https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf
It has more details on interfacing LVDS or LVPECL here for the clock input - and a lot of other good information.


Cheers,
bt

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tchin123
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Registered: ‎05-14-2017

The ZCu106 and ZCU102 development board uses the interface on UG576 page 327 (LVDS) for the si5328 clock output to the FPGA mgt_clk pin. After running the DSPLLsim software for the Si5328 clock driver, it generated a LVPECL format instead of the LVDS. 

Ii is possible that the LVPECL might work, but I'll keep this in mind and switch to LVDS if this give me problem. Either way Xilinx should provide an IOSTANDARD for the mgt_clk because it is easier to modify the xdc file then re-programming the Si5328 and incorporating the register map again into the FPGA design.

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barriet
Xilinx Employee
Xilinx Employee
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Registered: ‎08-13-2007

That's my point - I guess I didn't make it clear.
When you apply an IOSTANDARD to a SelectIO - it is actually changing the configuration of the input buffer, output buffer, etc. in the FPGA configuration.
There is no such flexibility with the GTs - that's why the GT user guides have different recommendations externally (board-level) depending on if the reference clock is LVDS or LVPECL.

There is no FPGA-level programmability on the IOSTANDARD here - that's why it isn't needed or provided.

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