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rohitmusalay009
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Registered: ‎06-06-2011

multiple FPGA JTAG interface.

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hello all,

 

am interfacing 4 individually removable FPGAs + PROMs daughter boards on a motherboard. each daughter board has it's own JTAG connector and the motherboard also has one for when they are working in parallel.

need a simple logic for the JTAG signals for implementing the chain.

 

parameters:

 

1) out of the 4, any number of FPGAs, not necessarily in series, may be inserted. eg.FPGA 2 and FPGA  4

 

2) the TDI signal from main JTAG has been connected to a series of 2:1 MUXes which route it to the first FPGA in the chain.

 

3) the TCK and TMS signals have been made common for all FPGAs.

 

4) the TDO signals (of each FPGA) have 3 paths:

    

       a) back to daughter borad FPGA JTAG connector when removed from motherborad and being programmed                individually.

 

       b) to the TDI of the next FPGA in series.

 

       c) back to the TDO of the main motherboard JTAG connector.---when it is the last FPGA in the chain.

(have used a 4:1 demux for this.......4 TDO signals,one from each FPGA) 

 

on the daughter board:

a) the TCK and TMS signals are permanently connected to the daughter board JTAG.

 

b) the TDI signal can come from 1 of 2 paths

    

    i) the TDO of the preceding FPGA.

                     or

    ii) the TDI of the daughter board JTAG connector.

(have used a 2:1 MUX for this.)

 

i'm hoping the design can be simplified.

 

am attaching a half done drawing.please note the daughter board JTAG connection has not been shown.

 

regards.

 

JTAG CHAIN MULTI FPGA xiilinx.jpg
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tmcdowe
Xilinx Employee
Xilinx Employee
12,247 Views
Registered: ‎12-17-2007

make sure you follow this information when using a JTAG mux: http://www.xilinx.com/support/answers/16832.htm

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drjohnsmith
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Registered: ‎07-09-2009

don't understand if there is a question there.

 

normal way of this sort of problem is TDO ( Test data out ) of one device goes to the TDI ( Test Data In) of ther next device.

 

forming a chain.

 

TCK ( Test Clock ) , TMS ( Test Mode Select ) are common to all devices.

  

If you have a few devices, TCK and TMS tend to be buffered,

 

and if you have devices that can be in / out the circuit, like a daughter board.

   a mux is used to switch the TDI / TDO pins of that device out of circuit.

      it does not matter if TCK and TMS are still left connected.

 

http://www.xilinx.com/support/documentation/application_notes/xapp544.pdf

 

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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rohitmusalay009
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Registered: ‎06-06-2011

the problem was to figure out a logic for any and all combinations of the FPGAs, as i have mentioned above.

i realise the chain(tdo,tdi) has to be complete......that has been done by muxes.

 

i wanted to be able to achieve stand-alone operation (for each FPGA) while the FPGA was "plugged in"....

 

thank you for your reply sir.

 

i think i found my solution in JTAG MUXes.

 

regards,

rohit.

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drjohnsmith
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Registered: ‎07-09-2009

and dont forget,

    that you can talk to any individual JTAG chip, without the others being affected.

 

The JTAG spec supports putting each device into JTAG bypass, 

     so provided the JTAG device is present you don't need to mux it out.

 

helps make JTAG chains easy to use and debug with.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
tmcdowe
Xilinx Employee
Xilinx Employee
12,248 Views
Registered: ‎12-17-2007

make sure you follow this information when using a JTAG mux: http://www.xilinx.com/support/answers/16832.htm

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rohitmusalay009
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Registered: ‎06-06-2011

thanks a lot.

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ciaoci
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Registered: ‎04-27-2012

Hi all,

 

what about the VREF and GND signals? I suppose GND common to all devices (like TCK and TMS), and VREF?

 

Any recommendation on cable/wires length? I would like to have a chan of 8 boards (with a couple of FPHA/FLASH each).

 

Cheers and thanks for any answers

 

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